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* interchange: tests: add obuftds testAlessandro Comodi2021-07-066-0/+80
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #748 from acomodi/fix-phys-net-writinggatecat2021-07-021-2/+13
|\ | | | | interchange: phys: skip only nets writing on disconnected out ports
| * interchange: phys: skip only nets writing on disconnected out portsAlessandro Comodi2021-07-021-2/+13
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #747 from cr1901/machxo2gatecat2021-07-019-13/+140
|\ | | | | MachXO2 Checkpoint 1
| * machxo2: Fix packing for directly-connected DFFs.William D. Jones2021-07-013-9/+28
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| * machxo2: Add VHDL primitives, demo, and script.William D. Jones2021-07-014-0/+81
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| * machxo2: Add a special case for pips whose config bits are in multipleWilliam D. Jones2021-07-011-0/+12
| | | | | | | | tiles.
| * machxo2: Hardcode a rule for emitting U_/D_ or G_ prefixes in ASCII output.William D. Jones2021-07-011-2/+17
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| * machxo2: Set Pip and Wire delays to reasonable fake values mirroringWilliam D. Jones2021-07-011-2/+2
| | | | | | | | estimateDelay.
* | Merge pull request #746 from YosysHQ/gatecat/ic-can-invert-constgatecat2021-07-011-5/+9
|\ \ | | | | | | interchange: Handle canInvert PIPs when processing preferred constants
| * | interchange: Handle canInvert PIPs when processing preferred constantsgatecat2021-07-011-5/+9
| |/ | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #745 from YosysHQ/gatecat/ic-node-sourcegatecat2021-07-011-0/+5
|\ \ | |/ |/| interchange: Handle case where routing source is a node
| * interchange: Handle case where routing source is a nodegatecat2021-07-011-0/+5
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-07-011-1/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #744 from YosysHQ/gatecat/const-in-macrogatecat2021-07-011-1/+1
|\ | | | | interchange: Fix handling of constants in macros
| * interchange: Fix handling of constants in macrosgatecat2021-07-011-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #743 from YosysHQ/gatecat/site-rsv-portsgatecat2021-07-015-0/+69
|\ \ | | | | | | interchange: Reserve site ports only reachable from dedicated routing
| * | interchange: Reserve site ports only reachable from dedicated routinggatecat2021-07-015-0/+69
| |/ | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #742 from acomodi/interchange-do-not-output-zero-user-netsgatecat2021-07-011-1/+12
|\ \ | |/ |/| interchange: phys: do not output nets which have no users
| * interchange: phys: do not output nets which have no usersAlessandro Comodi2021-07-011-1/+12
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #741 from acomodi/fix-ded-intercgatecat2021-06-301-8/+14
|\ | | | | interchange: fix dedicated interconnect exploration
| * interchange: fix dedicated interconnect explorationAlessandro Comodi2021-06-301-8/+14
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #739 from YosysHQ/gatecat/usp-io-macrogatecat2021-06-305-1/+91
|\ | | | | interchange: Place entire IO macro based on routeability
| * interchange: Fix dedicated interconnect check when site is the samegatecat2021-06-301-1/+4
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Place IO macro content based on routinggatecat2021-06-301-0/+79
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Track the macros that cells have been expanded fromgatecat2021-06-293-0/+8
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #738 from YosysHQ/json_load_reinitgatecat2021-06-303-11/+11
|\ \ | | | | | | Preserve ArchArgs and reinit Context when applicable in GUI, fixes #737
| * | Preserve ArchArgs and reinit Context when applicable in GUIMiodrag Milanovic2021-06-303-11/+11
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* / loading json should be disabled in this placeMiodrag Milanovic2021-06-301-1/+1
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* Merge pull request #736 from YosysHQ/gatecat/pp-multi-outputgatecat2021-06-281-13/+2
|\ | | | | interchange: Allow site wires driven by more than one bel
| * interchange: Allow site wires driven by more than one belgatecat2021-06-281-13/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #735 from YosysHQ/gatecat/ic-disconn-belpingatecat2021-06-281-1/+1
|\ \ | |/ |/| interchange: Handle disconnected bel pins in dedicated interconnect
| * interchange: Handle disconnected bel pins in dedicated interconnectgatecat2021-06-281-1/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #734 from acomodi/remove-rw-patchgatecat2021-06-241-3/+0
|\ | | | | ci: remove RapidWright patching
| * ci: remove RapidWright patchingAlessandro Comodi2021-06-241-3/+0
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #733 from acomodi/interchange-move-macro-before-iogatecat2021-06-181-1/+1
|\ | | | | interchange: arch: move macro expansion step before ios packing
| * interchange: arch: move macro expansion step before ios packingAlessandro Comodi2021-06-181-1/+1
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #731 from YosysHQ/gatecat/timing-mem-errorgatecat2021-06-171-4/+11
|\ | | | | sta: Fix a memory error introduced by using dict instead of unordered_map
| * sta: Fix a memory error introduced by the dict movegatecat2021-06-171-4/+11
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #730 from YosysHQ/gatecat/dcc-routehtrugatecat2021-06-173-3/+62
|\ | | | | nexus: Fix some 17k reliability issues
| * nexus: Disable center DCC-thrus on 17k devicegatecat2021-06-163-1/+29
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * nexus: Fix FASM gen for DCC-thrugatecat2021-06-161-3/+34
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #728 from YosysHQ/gatecat/nexus-ramgatecat2021-06-157-2/+384
|\ | | | | interchange/nexus: Add RAM techmap rule and a RAM test
| * interchange: Bump versionsgatecat2021-06-151-2/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * nexus: Add modified version of RAM testgatecat2021-06-155-0/+206
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * nexus: Add PDPSC16K->PDPSC16K_MODE to remap rulesgatecat2021-06-151-0/+176
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #729 from acomodi/interchange-fix-phys-net-writergatecat2021-06-151-5/+2
|\ \ | | | | | | interchange: fix phys net writer
| * | interchange: fix phys net writerAlessandro Comodi2021-06-151-5/+2
|/ / | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #727 from YosysHQ/gatecat/ic-undrivengatecat2021-06-143-5/+9
|\| | | | | interchange: Cope with undriven nets in more places
| * interchange: Cope with undriven nets in more placesgatecat2021-06-143-5/+9
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>