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| author | gatecat <gatecat@ds0.me> | 2021-07-01 15:28:16 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-01 15:28:16 +0100 |
| commit | 344cfe6216f0f0cf02dd9d130af51f93b3d4e6df (patch) | |
| tree | afbadb03a41b9bbc41a935c8974a5124026eadcd | |
| parent | 86bc708299be1bdaf964c42ebb28dc51d91b75c5 (diff) | |
| parent | f17643bc082307211af39919008e83d7b1b9a83d (diff) | |
| download | nextpnr-344cfe6216f0f0cf02dd9d130af51f93b3d4e6df.tar.gz nextpnr-344cfe6216f0f0cf02dd9d130af51f93b3d4e6df.tar.bz2 nextpnr-344cfe6216f0f0cf02dd9d130af51f93b3d4e6df.zip | |
Merge pull request #745 from YosysHQ/gatecat/ic-node-source
interchange: Handle case where routing source is a node
| -rw-r--r-- | fpga_interchange/fpga_interchange.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/fpga_interchange/fpga_interchange.cpp b/fpga_interchange/fpga_interchange.cpp index 89f1f958..92d409f9 100644 --- a/fpga_interchange/fpga_interchange.cpp +++ b/fpga_interchange/fpga_interchange.cpp @@ -313,6 +313,11 @@ static void emit_net( // FIXME: Consider making sure that wire_data.bel_pins[0] is always the // source BEL pin in the BBA generator. static BelPin find_source(const Context *ctx, WireId source_wire) { + if (source_wire.tile == -1) { + // Nodal wire, probably a constant, cannot have an associated bel pin + return BelPin(); + } + const TileTypeInfoPOD & tile_type = loc_info(ctx->chip_info, source_wire); const TileWireInfoPOD & wire_data = tile_type.wire_data[source_wire.index]; |