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* router2: Reserve source wire, toogatecat2022-09-201-0/+7
* fabulous: fix, but disable, IO configurationgatecat2022-09-161-0/+3
* Merge pull request #1026 from YosysHQ/gatecat/ecp5-bitstream-refactormyrtle2022-09-161-1347/+1402
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| * ecp5: Split bitstream generation into more functionsgatecat2022-09-151-1347/+1402
* | Merge pull request #1023 from YosysHQ/gatecat/ice40up-bram-polmyrtle2022-09-161-3/+7
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| * | ice40: Fix UltraPlus BRAM clock polaritygatecat2022-09-141-3/+7
* | | Merge pull request #1025 from YosysHQ/gatecat/nexus-dev-fixesmyrtle2022-09-153-1/+42
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| * | nexus: Add ES2 device names and --list-devicesgatecat2022-09-153-1/+42
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* | Merge pull request #1015 from YosysHQ/gatecat/fabulous-viaductmyrtle2022-09-1512-1/+1637
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| * | fabulous: Add a viaduct uarchgatecat2022-09-0912-1/+1637
* | | Merge pull request #1024 from YosysHQ/gatecat/pybind11-bumpmyrtle2022-09-15214-10025/+21644
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| * | 3rdparty: Bump vendored pybind11 version for py3.11 supportgatecat2022-09-14214-10025/+21644
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* | Merge pull request #1018 from yrabbit/bf-0myrtle2022-08-251-0/+2
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| * | gowin: BUGFIX. Really memorize the chipYRabbit2022-08-251-0/+2
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* | Merge pull request #1017 from YosysHQ/routerfixmyrtle2022-08-222-5/+4
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| * | add missing overridesMiodrag Milanovic2022-08-221-3/+3
| * | Fix parameter orderMiodrag Milanovic2022-08-221-2/+1
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* | Merge pull request #1016 from atsampson/python3myrtle2022-08-217-16/+16
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| * | Use CMake's Python3 rather than PythonInterp in subdirsAdam Sampson2022-08-217-16/+16
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* | pybindings: Mark CellInfo::bel as readonlygatecat2022-08-181-2/+1
* | Merge pull request #1014 from LAK132/mastermyrtle2022-08-181-4/+4
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| * Replace deprecated method of finding Python 3LAK1322022-08-171-4/+4
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* Merge pull request #1013 from YosysHQ/gatecat/viaduct-argsmyrtle2022-08-151-0/+14
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| * viaduct: Allow passing command line options to uarch with -ogatecat2022-08-151-0/+14
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* Merge pull request #1012 from YosysHQ/gatecat/refactor-id-inmyrtle2022-08-1124-203/+153
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| * refactor: Use IdString::in instead of || chainsgatecat2022-08-1024-203/+153
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* Merge pull request #1011 from YosysHQ/gatecat/nexus-lram-tmgmyrtle2022-08-103-0/+30
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| * nexus: Add timing data for LRAMgatecat2022-08-103-0/+30
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* Merge pull request #1010 from YosysHQ/gatecat/idfmyrtle2022-08-1022-153/+152
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| * refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-1022-153/+152
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* Merge pull request #1008 from YosysHQ/gatecat/generic-addbelpinmyrtle2022-08-043-25/+12
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| * generic: addBelPin with direction as an arggatecat2022-08-043-25/+12
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* Merge pull request #1004 from yrabbit/fix-muxesmyrtle2022-07-217-38/+26
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| * Merge branch 'master' into fix-muxesYRabbit2022-07-201-1/+1
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* | Merge pull request #1005 from YosysHQ/gatecat/nexus-ram-fixesmyrtle2022-07-191-1/+1
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| * | nexus: Fix CSDECODE parsinggatecat2022-07-191-1/+1
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| * gowin: fix compilationYRabbit2022-07-191-8/+0
| * gowin: Remove incomprehensible names of the muxesYRabbit2022-07-197-34/+30
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* Merge pull request #998 from yrabbit/clock-wipmyrtle2022-07-186-1/+479
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| * Merge branch 'master' into clock-wipYRabbit2022-07-1016-49/+198
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* | Merge pull request #999 from YosysHQ/gatecat/pseudocell-apimyrtle2022-07-0816-49/+198
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| * | netlist: Add PseudoCell APIgatecat2022-07-0816-49/+198
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| * gowin: Remove unnecessary functionsYRabbit2022-07-052-33/+9
| * Merge branch 'master' into clock-wipYRabbit2022-07-059-106/+211
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* | Merge pull request #995 from pepijndevos/shadowrammyrtle2022-07-056-0/+187
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| * | use DFF RAM modePepijn de Vos2022-07-021-1/+4
| * | Merge branch 'master' into shadowramPepijn de Vos2022-07-029-25/+324
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| * | | hook up CE maybePepijn de Vos2022-06-163-0/+4
| * | | lutram actually PnRsPepijn de Vos2022-06-065-38/+43
| * | | WIP shadowramPepijn de Vos2022-06-056-0/+175