aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* mistral: Carry debugginggatecat2021-05-153-41/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Write arith mode to bitstream (not yet functional)gatecat2021-05-152-2/+18
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: First pass at carry packinggatecat2021-05-154-8/+82
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: FF validity checking fixesgatecat2021-05-151-7/+13
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Fix constant trimminggatecat2021-05-152-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Write LUT initsgatecat2021-05-152-1/+72
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add some IO configurationgatecat2021-05-151-0/+30
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Setting some more boilerplate bitsgatecat2021-05-153-1/+118
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add stub RBF generationgatecat2021-05-154-9/+108
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Rename clock buffer primitivegatecat2021-05-152-2/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Python and GUI stubgatecat2021-05-156-0/+350
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Implement some misc. thingsgatecat2021-05-154-10/+78
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Some preps for generating bitstreamsgatecat2021-05-154-28/+131
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Adding a function for computing ALM LUT masksgatecat2021-05-152-0/+90
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add IO packinggatecat2021-05-155-8/+135
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add a basic QSF parsergatecat2021-05-154-1/+295
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add some packing logic based on nexusgatecat2021-05-154-3/+202
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Working on FF validity checkinggatecat2021-05-152-1/+117
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add the 'pin style' stuff based on Nexusgatecat2021-05-152-0/+112
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Working on ALM input assignmentgatecat2021-05-152-2/+118
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add stub pack/place/route functionsgatecat2021-05-155-5/+143
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Renamed arch from cyclonevgatecat2021-05-159-4/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Rebase updategatecat2021-05-151-1/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: More validity checking thoughtsgatecat2021-05-155-7/+49
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Add validity check and IO belsgatecat2021-05-155-9/+92
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: First (untested) pass at ALM validity checkinggatecat2021-05-152-40/+135
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: More preparations for validity checkinggatecat2021-05-155-7/+159
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Preparations for validity checkinggatecat2021-05-152-0/+37
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Fix some archcheck failsgatecat2021-05-153-4/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Rework belsgatecat2021-05-153-97/+76
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Outline LAB structuregatecat2021-05-154-4/+207
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Outline functions for creating bels/wires/pipsgatecat2021-05-152-3/+104
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* archcheck: Use old connectivity check for CycloneVgatecat2021-05-151-1/+29
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Add routing graphgatecat2021-05-152-4/+73
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Add names and archcheck fixesgatecat2021-05-155-54/+138
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Add some range typesgatecat2021-05-151-7/+69
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Add enough stubs that it linksgatecat2021-05-154-28/+147
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Add wire and pip typesgatecat2021-05-152-12/+45
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Add some useful constidsgatecat2021-05-153-0/+76
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Update in line with nextpnr changesgatecat2021-05-155-239/+128
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* build bel list in constructorDan Ravensloft2021-05-152-44/+35
|
* current progressDan Ravensloft2021-05-153-23/+118
|
* bind/unbind belDan Ravensloft2021-05-152-0/+36
|
* Resolve feedbackDan Ravensloft2021-05-153-7/+7
|
* couple of functions implementedDan Ravensloft2021-05-153-234/+114
|
* cyclonev: basic platformDan Ravensloft2021-05-155-1/+579
|
* Merge pull request #706 from acomodi/fix-illegal-site-thrugatecat2021-05-143-21/+62
|\ | | | | interchange: pseudo pips: fix illegal tile pseudo PIPs
| * interchange: pseudo pips: fix illegal tile pseudo PIPsAlessandro Comodi2021-05-143-21/+62
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #700 from acomodi/fix-illegal-site-thrugatecat2021-05-133-16/+58
|\ | | | | interchange: arch: do not allow site pips within sites
| * interchange: site router: add valid pips list to check during routingAlessandro Comodi2021-05-133-11/+59
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-04 01:14:14 +0000