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* Merge pull request #155 from smunaut/issue_151David Shah2018-11-281-48/+48
|\ | | | | ice40: Update the way LVDS inputs are handled during bitstream generation
| * ice40: Update the way LVDS inputs are handled during bitstream generationSylvain Munaut2018-11-281-48/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Instead of "patching" input_en, we completely separate config for normal and LVDS pair. - For normal pair, nothing changes - For LVDS pairs, the IE/REN bits are always set as if the input buffer are disabled. Then if input_en was set to 1 (i.e. the input is actually for something), then we set the IoCtrl.LVDS bit. - Also for LVDS, if input is used, pullups are forcibly disabled. * When scanning for unused IOs, never process those part of a LVDS pair. They will have been configured by the complement Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #154 from smunaut/issue_141David Shah2018-11-281-72/+212
|\ \ | |/ |/| ice40: Complete rework of the way PLLs are placed and validity checks
| * ice40: Try to be helpful and suggest using PAD PLL instead of CORESylvain Munaut2018-11-281-2/+14
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * ice40: Revamp the whole PLL placement/validity check logicSylvain Munaut2018-11-281-72/+200
|/ | | | | | | | | | | | | | | | | We do a pre-pass on all the PLLs to place them before packing. To place them: - First pass with all the PADs PLLs since those can only fit at one specific BEL depending on the input connection - Second pass with all the dual outputs CORE PLLs. Those can go anywhere where there is no conflicts with their A & B outputs and used IO pins - Third pass with the single output CORE PLLs. Those have the least constrains. During theses passes, we also check the validity of all their connections. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Merge pull request #153 from YosysHQ/global-optionsDavid Shah2018-11-282-3/+14
|\ | | | | ice40: Finer-grained control of global promotion
| * ice40: Finer-grained control of global promotionDavid Shah2018-11-272-3/+14
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #152 from YosysHQ/compile_fixDavid Shah2018-11-271-0/+10
|\ | | | | Fix compile on GCC 5.5 or older
| * Fix compile on GCC 5.5 or olderMiodrag Milanovic2018-11-271-0/+10
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* Merge pull request #150 from YosysHQ/err_warn_countDavid Shah2018-11-264-2/+19
|\ | | | | Print warning and error count at end of execution
| * Print warning and error count at end of executionDavid Shah2018-11-264-2/+19
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* timing: Improve clock constraint log outputDavid Shah2018-11-261-2/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #149 from smunaut/issue_148David Shah2018-11-264-10/+43
|\ | | | | Fixes for global promotion
| * ice40: During global promotion, only promote if this will actually fit !Sylvain Munaut2018-11-261-6/+32
| | | | | | | | | | | | | | | | We need to take into account the global networks that are already used and possibly locked to know what we can promote since all networks can't drive resets / clock-enables Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * ice40: Add helper to know which global network is driven by a SB_GB BelSylvain Munaut2018-11-262-2/+8
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * placer1: During initial placement, don't rip-up strongly binded cellsSylvain Munaut2018-11-261-2/+3
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ecp5: Fix UR PLL tile coordinatesDavid Shah2018-11-261-2/+2
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Update README.mdDavid Shah2018-11-261-4/+6
| | | | | | Fixes #74 Signed-off-by: David Shah <dave@ds0.me>
* clangformatDavid Shah2018-11-261-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #143 from daveshah1/ecp5_muxesDavid Shah2018-11-265-6/+169
|\ | | | | ecp5: Adding support for LUT extension muxes up to LUT7
| * ecp5: Add support for LUT7 muxDavid Shah2018-11-181-6/+116
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: More optimal LUT6 placementDavid Shah2018-11-163-1/+11
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Adding mux support up to LUT6David Shah2018-11-163-6/+49
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #138 from YosysHQ/refactor_logDavid Shah2018-11-268-123/+84
|\ \ | | | | | | Tidy up logging code, add log file support, make timing failures non-fatal errors
| * | Add nonfatal error support and use for timing failuresDavid Shah2018-11-264-3/+14
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | Change the log level of some timing-related messagesDavid Shah2018-11-213-16/+20
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | Refactor log code and add log file supportDavid Shah2018-11-215-106/+52
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #139 from YosysHQ/fix_117David Shah2018-11-261-1/+6
|\ \ \ | | | | | | | | router1: Fix unrouted, undriven nets
| * | | router1: Fix unrouted, undriven netsDavid Shah2018-11-211-1/+6
| |/ / | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | json: Remove superfluous floating node messageDavid Shah2018-11-261-5/+0
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ice40: Improve PCF error handlingDavid Shah2018-11-261-3/+9
| | | | | | | | | | | | | | | | | | Fixes #147 Signed-off-by: David Shah <dave@ds0.me>
* | | Merge branch 'master' of github.com:YosysHQ/nextpnrDavid Shah2018-11-262-1/+3
|\ \ \
| * \ \ Merge pull request #146 from YosysHQ/fix_145David Shah2018-11-241-0/+2
| |\ \ \ | | | | | | | | | | ice40: Fix disconnection of PACKAGEPIN for PAD PLLs
| | * | | ice40: Fix disconnection of PACKAGEPIN for PAD PLLsDavid Shah2018-11-241-0/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | Merge pull request #144 from bgamari/patch-1David Shah2018-11-221-1/+1
| |\ \ \ \ | | |/ / / | |/| | | docs/constraints: Fix typo
| | * | | docs/constraints: Fix typoBen Gamari2018-11-221-1/+1
| |/ / /
* / / / python: Fixes to get net wires map workingDavid Shah2018-11-223-4/+55
|/ / / | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | python: Add wrapper for vectors to allow Python access to net.usersDavid Shah2018-11-223-4/+76
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #122 from YosysHQ/ecp5_timingDavid Shah2018-11-229-134/+372
|\ \ \ | | |/ | |/| ecp5: Use cell and pip timings from the Trellis database
| * | timing: Improve crit path statisticsDavid Shah2018-11-161-2/+7
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Add 10% safety margin to pip delaysDavid Shah2018-11-161-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: clangformat timing changesDavid Shah2018-11-164-19/+18
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Use speed-grade-specific delay estimateDavid Shah2018-11-162-3/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Fix db import, improve timing data debuggingDavid Shah2018-11-164-5/+55
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Allow selection of device speed gradeDavid Shah2018-11-161-3/+26
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Post-rebase fixDavid Shah2018-11-161-3/+3
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Consider fanout when calculating pip delaysDavid Shah2018-11-161-2/+12
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Fix timing pip classesDavid Shah2018-11-161-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Use new timing dataDavid Shah2018-11-164-94/+82
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Fix timing data importDavid Shah2018-11-161-5/+16
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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