timing: Improve clock constraint log output

Signed-off-by: David Shah <dave@ds0.me>

1 files changed, 6 insertions, 2 deletions

diff --git a/common/nextpnr.cc b/common/nextpnr.cc
index be3bfe14..bb941d3d 100644
--- a/common/nextpnr.cc
+++ b/common/nextpnr.cc
@@ -409,12 +409,16 @@ void Context::check() const
 
 void BaseCtx::addClock(IdString net, float freq)
 {
-    log_info("constraining clock net '%s' to %.02f MHz\n", net.c_str(this), freq);
     std::unique_ptr<ClockConstraint> cc(new ClockConstraint());
     cc->period = getCtx()->getDelayFromNS(1000 / freq);
     cc->high = getCtx()->getDelayFromNS(500 / freq);
     cc->low = getCtx()->getDelayFromNS(500 / freq);
-    nets.at(net)->clkconstr = std::move(cc);
+    if (!nets.count(net)) {
+        log_warning("net '%s' does not exist in design, ignoring clock constraint\n", net.c_str(this));
+    } else {
+        nets.at(net)->clkconstr = std::move(cc);
+        log_info("constraining clock net '%s' to %.02f MHz\n", net.c_str(this), freq);
+    }
 }
 
 NEXTPNR_NAMESPACE_END