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* ci: Restructure and move entirely to GH actions from Cirrusgatecat2022-04-081-68/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Split the SLICE bel into separate LUT/FF/RAMW belsgatecat2022-04-071-1/+1
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* ice40: Merge driving LUT<=2s into carry-only LCsgatecat2022-03-291-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: bump apycula versionVerneri Hirvonen2022-02-161-1/+1
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* add GW1N-9C dbPepijn de Vos2022-02-061-1/+1
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* update release that actually includes GW1NS-4 chipdbPepijn de Vos2021-12-261-1/+1
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* build on release of apycula with gw1ns-4 supportPepijn de Vos2021-12-241-1/+1
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* ecp5: LUT permutation supportgatecat2021-12-131-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: use latest Apycula releaseYRabbit2021-11-071-1/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* ci: Bump prjoxide versiongatecat2021-09-241-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* .cirrus/Dockerfile.ubuntu20.04: update apycula to 0.0.1a9Gwenhael Goavec-Merou2021-07-061-1/+1
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* Add libcapnp-dev for FPGA interchange compilation support.Keith Rothman2021-02-151-1/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* ci: Bump prjtrellis versiongatecat2021-02-121-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Update prjoxide URLD. Shah2021-02-081-1/+1
| | | | Signed-off-by: D. Shah <gatecat@ds0.me>
* Merge pull request #553 from YosysHQ/rel-sliceDavid Shah2021-01-281-1/+1
|\ | | | | Switch from RelPtr to RelSlice
| * nexus: Switch from RelPtr to RelSliceD. Shah2021-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | This replaces RelPtrs and a separate length field with a Rust-style slice containing both a pointer and a length; with bounds checking always enforced. Thus iterating over these structures is both cleaner and safer. Signed-off-by: D. Shah <dave@ds0.me>
* | Gowin: Add GW1N-4 supportPepijn de Vos2021-01-031-1/+1
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* Gowin target (#542)Pepijn de Vos2020-12-301-0/+67
* load wires * add slice bels * add IOB * add aliases * local aliases * broken packing stuff * working packer * add constraints * pnr runs1111 * add timing info * constraints * more constraint stuff * add copyright * remove generic reference * remove parameters * remove generic python api * add newline to end of file * some small refactoring * warn on invalid constraints * don't error on missing cell * comment out debugging print * typo * avoid copy * faster empty idstring * remove intermediate variable * no more deadnames * fix cst warnings * increase ripup and epsilon a bit * take single device parameter * add info to readme * gui stubs * Revert 4d03b681a8634e978bd5af73c97665500047e055 * assign ff_used in assignArchInfo * decrease beta for better routability * try to fix CI
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