3 files changed, 14 insertions, 1 deletions
diff --git a/fpga_interchange/examples/tests/counter/CMakeLists.txt b/fpga_interchange/examples/tests/counter/CMakeLists.txt
index 60375770..0da62934 100644
--- a/fpga_interchange/examples/tests/counter/CMakeLists.txt
+++ b/fpga_interchange/examples/tests/counter/CMakeLists.txt
@@ -5,6 +5,7 @@ add_interchange_test(
     tcl run.tcl
     xdc counter_basys3.xdc
     sources counter.v
+    techmap remap.v
 )
 
 add_interchange_test(
@@ -14,4 +15,5 @@ add_interchange_test(
     tcl run.tcl
     xdc counter_arty.xdc
     sources counter.v
+    techmap remap.v
 )
diff --git a/fpga_interchange/examples/tests/counter/remap.v b/fpga_interchange/examples/tests/counter/remap.v
new file mode 100644
index 00000000..6dfc0b4a
--- /dev/null
+++ b/fpga_interchange/examples/tests/counter/remap.v
@@ -0,0 +1,11 @@
+module INV(input I, output O);
+
+LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
+
+endmodule
+
+module BUF(input I, output O);
+
+LUT1 #(.INIT(2'b10)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
+
+endmodule
diff --git a/fpga_interchange/examples/tests/counter/run.tcl b/fpga_interchange/examples/tests/counter/run.tcl
index 7cd9f10f..ffea3b2e 100644
--- a/fpga_interchange/examples/tests/counter/run.tcl
+++ b/fpga_interchange/examples/tests/counter/run.tcl
@@ -3,7 +3,7 @@ yosys -import
 read_verilog $::env(SOURCES)
 
 synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
-techmap -map ../remap.v
+techmap -map $::env(TECHMAP)
 
 # opt_expr -undriven makes sure all nets are driven, if only by the $undef
 # net.