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Diffstat (limited to 'fpga_interchange/examples/tests/counter/run.tcl')
| -rw-r--r-- | fpga_interchange/examples/tests/counter/run.tcl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga_interchange/examples/tests/counter/run.tcl b/fpga_interchange/examples/tests/counter/run.tcl index 7cd9f10f..ffea3b2e 100644 --- a/fpga_interchange/examples/tests/counter/run.tcl +++ b/fpga_interchange/examples/tests/counter/run.tcl @@ -3,7 +3,7 @@ yosys -import read_verilog $::env(SOURCES) synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp -techmap -map ../remap.v +techmap -map $::env(TECHMAP) # opt_expr -undriven makes sure all nets are driven, if only by the $undef # net. |