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authorDavid Shah <davey1576@gmail.com>2018-08-08 14:37:59 +0200
committerDavid Shah <davey1576@gmail.com>2018-08-08 14:37:59 +0200
commitbf42e525cb7ab6ae071b16dfeca55194878be69c (patch)
treec9282e371fc57a71550e1dcca0ae9e38724d5bf4 /ice40/arch.h
parenta0994d515454a696c98602980b298ee61aa03f4e (diff)
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Arch API: New specification for timing port classes
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'ice40/arch.h')
-rw-r--r--ice40/arch.h6
1 files changed, 2 insertions, 4 deletions
diff --git a/ice40/arch.h b/ice40/arch.h
index a5be7e33..7cc8495d 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -788,10 +788,8 @@ struct Arch : BaseCtx
// Get the delay through a cell from one port to another, returning false
// if no path exists
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
- // Get the associated clock to a port, or empty if the port is combinational
- IdString getPortClock(const CellInfo *cell, IdString port) const;
- // Return true if a port is a clock
- bool isClockPort(const CellInfo *cell, IdString port) const;
+ // Get the port class, also setting clockDomain if applicable
+ TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockDomain) const;
// Return true if a port is a net
bool isGlobalNet(const NetInfo *net) const;
// Return true if a cell is an IO