From bf42e525cb7ab6ae071b16dfeca55194878be69c Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 8 Aug 2018 14:37:59 +0200 Subject: Arch API: New specification for timing port classes Signed-off-by: David Shah --- ice40/arch.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'ice40/arch.h') diff --git a/ice40/arch.h b/ice40/arch.h index a5be7e33..7cc8495d 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -788,10 +788,8 @@ struct Arch : BaseCtx // Get the delay through a cell from one port to another, returning false // if no path exists bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const; - // Get the associated clock to a port, or empty if the port is combinational - IdString getPortClock(const CellInfo *cell, IdString port) const; - // Return true if a port is a clock - bool isClockPort(const CellInfo *cell, IdString port) const; + // Get the port class, also setting clockDomain if applicable + TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockDomain) const; // Return true if a port is a net bool isGlobalNet(const NetInfo *net) const; // Return true if a cell is an IO -- cgit v1.2.3