Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pll

1 files changed, 15 insertions, 25 deletions

diff --git a/ice40/arch.cc b/ice40/arch.cc
index 5c632faa..1d7e9546 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -292,23 +292,6 @@ BelRange Arch::getBelsByTile(int x, int y) const
     return br;
 }
 
-BelRange Arch::getBelsAtSameTile(BelId bel) const
-{
-    BelRange br;
-    NPNR_ASSERT(bel != BelId());
-    int x = chip_info->bel_data[bel.index].x;
-    int y = chip_info->bel_data[bel.index].y;
-    int start = bel.index, end = bel.index;
-    while (start >= 0 && chip_info->bel_data[start].x == x && chip_info->bel_data[start].y == y)
-        start--;
-    start++;
-    br.b.cursor = start;
-    while (end < chip_info->num_bels && chip_info->bel_data[end].x == x && chip_info->bel_data[end].y == y)
-        end++;
-    br.e.cursor = end;
-    return br;
-}
-
 PortType Arch::getBelPinType(BelId bel, PortPin pin) const
 {
     NPNR_ASSERT(bel != BelId());
@@ -484,14 +467,6 @@ std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
 
 // -----------------------------------------------------------------------
 
-void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const
-{
-    NPNR_ASSERT(bel != BelId());
-    x = chip_info->bel_data[bel.index].x;
-    y = chip_info->bel_data[bel.index].y;
-    gb = chip_info->bel_data[bel.index].type == TYPE_SB_GB;
-}
-
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
 {
     NPNR_ASSERT(src != WireId());
@@ -735,6 +710,14 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
         } else if (fromPort == id("I2") && toPort == id("COUT")) {
             delay = 230;
             return true;
+        } else if (fromPort == id("CLK") && toPort == id("O")) {
+            delay = 540;
+            return true;
+        }
+    } else if (cell->type == id("ICESTORM_RAM")) {
+        if (fromPort == id("RCLK")) {
+            delay = 2140;
+            return true;
         }
     }
     return false;
@@ -745,6 +728,11 @@ IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
     if (cell->type == id("ICESTORM_LC") && bool_or_default(cell->params, id("DFF_ENABLE"))) {
         if (port != id("LO") && port != id("CIN") && port != id("COUT"))
             return id("CLK");
+    } else if (cell->type == id("ICESTORM_RAM")) {
+        if (port.str(this)[0] == 'R')
+            return id("RCLK");
+        else
+            return id("WCLK");
     }
     return IdString();
 }
@@ -753,6 +741,8 @@ bool Arch::isClockPort(const CellInfo *cell, IdString port) const
 {
     if (cell->type == id("ICESTORM_LC") && port == id("CLK"))
         return true;
+    if (cell->type == id("ICESTORM_RAM") && (port == id("RCLK") || (port == id("WCLK"))))
+        return true;
     return false;
 }