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| author | gatecat <gatecat@ds0.me> | 2022-02-18 12:07:49 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-18 12:07:49 +0000 |
| commit | 347ba3afb3f541edc594c8bc276cce481c7a7e03 (patch) | |
| tree | 28483964fb3c92bc104ab6162d1c9196651ced26 /generic/arch.cc | |
| parent | 61d1db16be2c68cf6ae8b4d2ff3266b5c7086ad2 (diff) | |
| parent | 6a32aca4ac8705b637943c236cedd2f36422fb21 (diff) | |
| download | nextpnr-347ba3afb3f541edc594c8bc276cce481c7a7e03.tar.gz nextpnr-347ba3afb3f541edc594c8bc276cce481c7a7e03.tar.bz2 nextpnr-347ba3afb3f541edc594c8bc276cce481c7a7e03.zip | |
Merge pull request #919 from YosysHQ/gatecat/netlist-iii
refactor: New member functions to replace design_utils
Diffstat (limited to 'generic/arch.cc')
| -rw-r--r-- | generic/arch.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/generic/arch.cc b/generic/arch.cc index ad054efd..c4814bab 100644 --- a/generic/arch.cc +++ b/generic/arch.cc @@ -721,7 +721,7 @@ void Arch::assignArchInfo() CellInfo *ci = cell.second.get(); if (ci->type == id("GENERIC_SLICE")) { ci->is_slice = true; - ci->slice_clk = get_net_or_empty(ci, id("CLK")); + ci->slice_clk = ci->getPort(id("CLK")); } else { ci->is_slice = false; } |