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| author | gatecat <gatecat@ds0.me> | 2021-04-25 16:29:13 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-05-21 10:00:35 +0100 |
| commit | 64f5b1d031960b779ca788d5fc92843c2213a045 (patch) | |
| tree | 481120d3b3ba5b09ecd7cb577ca7d52f41703c75 /fpga_interchange/site_arch.cc | |
| parent | a146dbdb03413ca32ca96c98ae5f3bdaf73d9126 (diff) | |
| download | nextpnr-64f5b1d031960b779ca788d5fc92843c2213a045.tar.gz nextpnr-64f5b1d031960b779ca788d5fc92843c2213a045.tar.bz2 nextpnr-64f5b1d031960b779ca788d5fc92843c2213a045.zip | |
interchange: Don't error out on missing cell ports
This is required for LUTRAM support, as the upper address bits of
RAMD64E etc are missing for shallower primitives.
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/site_arch.cc')
| -rw-r--r-- | fpga_interchange/site_arch.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/fpga_interchange/site_arch.cc b/fpga_interchange/site_arch.cc index 4438193b..ed2f6c8d 100644 --- a/fpga_interchange/site_arch.cc +++ b/fpga_interchange/site_arch.cc @@ -136,6 +136,8 @@ SiteArch::SiteArch(const SiteInformation *site_info) : ctx(site_info->ctx), site bool have_vcc_pins = false; for (CellInfo *cell : site_info->cells_in_site) { for (const auto &pin_pair : cell->cell_bel_pins) { + if (!cell->ports.count(pin_pair.first)) + continue; const PortInfo &port = cell->ports.at(pin_pair.first); if (port.net != nullptr) { nets.emplace(port.net, SiteNetInfo{port.net}); |