From 64f5b1d031960b779ca788d5fc92843c2213a045 Mon Sep 17 00:00:00 2001 From: gatecat Date: Sun, 25 Apr 2021 16:29:13 +0100 Subject: interchange: Don't error out on missing cell ports This is required for LUTRAM support, as the upper address bits of RAMD64E etc are missing for shallower primitives. Signed-off-by: gatecat --- fpga_interchange/site_arch.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'fpga_interchange/site_arch.cc') diff --git a/fpga_interchange/site_arch.cc b/fpga_interchange/site_arch.cc index 4438193b..ed2f6c8d 100644 --- a/fpga_interchange/site_arch.cc +++ b/fpga_interchange/site_arch.cc @@ -136,6 +136,8 @@ SiteArch::SiteArch(const SiteInformation *site_info) : ctx(site_info->ctx), site bool have_vcc_pins = false; for (CellInfo *cell : site_info->cells_in_site) { for (const auto &pin_pair : cell->cell_bel_pins) { + if (!cell->ports.count(pin_pair.first)) + continue; const PortInfo &port = cell->ports.at(pin_pair.first); if (port.net != nullptr) { nets.emplace(port.net, SiteNetInfo{port.net}); -- cgit v1.2.3