fpga_interchange: tests: add techmap optional source file

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

4 files changed, 19 insertions, 3 deletions

diff --git a/fpga_interchange/examples/tests.cmake b/fpga_interchange/examples/tests.cmake
index 9dc73add..899bfa4a 100644
--- a/fpga_interchange/examples/tests.cmake
+++ b/fpga_interchange/examples/tests.cmake
@@ -8,6 +8,7 @@ function(add_interchange_test)
     #    xdc <xdc>
     #    top <top name>
     #    sources <sources list>
+    #    [techmap <techmap file>]
     # )
     #
     # Generates targets to run desired tests
@@ -16,10 +17,10 @@ function(add_interchange_test)
     #   - test-fpga_interchange-<name>-json     : synthesis output
     #   - test-fpga_interchange-<name>-netlist  : interchange logical netlist
     #   - test-fpga_interchange-<name>-phys     : interchange physical netlist
-    #   - test-fpga_interchange-<name>-phys     : design checkpoint with RapidWright
+    #   - test-fpga_interchange-<name>-dcp     : design checkpoint with RapidWright
 
     set(options)
-    set(oneValueArgs name device package tcl xdc top)
+    set(oneValueArgs name device package tcl xdc top techmap)
     set(multiValueArgs sources)
 
     cmake_parse_arguments(
@@ -36,6 +37,7 @@ function(add_interchange_test)
     set(top ${add_interchange_test_top})
     set(tcl ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_tcl})
     set(xdc ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_xdc})
+    set(techmap ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_techmap})
 
     set(sources)
     foreach(source ${add_interchange_test_sources})
@@ -54,6 +56,7 @@ function(add_interchange_test)
         COMMAND
             SOURCES=${sources}
             OUT_JSON=${synth_json}
+            TECHMAP=${techmap}
             yosys -c ${tcl}
         DEPENDS ${sources}
     )
diff --git a/fpga_interchange/examples/tests/counter/CMakeLists.txt b/fpga_interchange/examples/tests/counter/CMakeLists.txt
index 60375770..0da62934 100644
--- a/fpga_interchange/examples/tests/counter/CMakeLists.txt
+++ b/fpga_interchange/examples/tests/counter/CMakeLists.txt
@@ -5,6 +5,7 @@ add_interchange_test(
     tcl run.tcl
     xdc counter_basys3.xdc
     sources counter.v
+    techmap remap.v
 )
 
 add_interchange_test(
@@ -14,4 +15,5 @@ add_interchange_test(
     tcl run.tcl
     xdc counter_arty.xdc
     sources counter.v
+    techmap remap.v
 )
diff --git a/fpga_interchange/examples/tests/counter/remap.v b/fpga_interchange/examples/tests/counter/remap.v
new file mode 100644
index 00000000..6dfc0b4a
--- /dev/null
+++ b/fpga_interchange/examples/tests/counter/remap.v
@@ -0,0 +1,11 @@
+module INV(input I, output O);
+
+LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
+
+endmodule
+
+module BUF(input I, output O);
+
+LUT1 #(.INIT(2'b10)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
+
+endmodule
diff --git a/fpga_interchange/examples/tests/counter/run.tcl b/fpga_interchange/examples/tests/counter/run.tcl
index 7cd9f10f..ffea3b2e 100644
--- a/fpga_interchange/examples/tests/counter/run.tcl
+++ b/fpga_interchange/examples/tests/counter/run.tcl
@@ -3,7 +3,7 @@ yosys -import
 read_verilog $::env(SOURCES)
 
 synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
-techmap -map ../remap.v
+techmap -map $::env(TECHMAP)
 
 # opt_expr -undriven makes sure all nets are driven, if only by the $undef
 # net.