fpga_interchange: tests: add cmake functions

Also move all tests in a tests directory

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

4 files changed, 0 insertions, 42 deletions

diff --git a/fpga_interchange/examples/ff/Makefile b/fpga_interchange/examples/ff/Makefile
deleted file mode 100644
index c6118ff7..00000000
--- a/fpga_interchange/examples/ff/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-DESIGN := ff
-DESIGN_TOP := top
-PACKAGE := csg324
-
-include ../template.mk
-
-build/ff.json: ff.v | build
-	yosys -c run.tcl
diff --git a/fpga_interchange/examples/ff/ff.v b/fpga_interchange/examples/ff/ff.v
deleted file mode 100644
index 1c271042..00000000
--- a/fpga_interchange/examples/ff/ff.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module top(input clk, input d, input r, output reg q);
-
-always @(posedge clk)
-begin
-    if(r)
-        q <= 1'b0;
-    else
-        q <= d;
-end
-
-endmodule
diff --git a/fpga_interchange/examples/ff/ff.xdc b/fpga_interchange/examples/ff/ff.xdc
deleted file mode 100644
index 3c132f1d..00000000
--- a/fpga_interchange/examples/ff/ff.xdc
+++ /dev/null
@@ -1,9 +0,0 @@
-set_property PACKAGE_PIN P17 [get_ports clk]
-set_property PACKAGE_PIN N15 [get_ports d]
-set_property PACKAGE_PIN N16 [get_ports r]
-set_property PACKAGE_PIN M17 [get_ports q]
-
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-set_property IOSTANDARD LVCMOS33 [get_ports d]
-set_property IOSTANDARD LVCMOS33 [get_ports r]
-set_property IOSTANDARD LVCMOS33 [get_ports q]
diff --git a/fpga_interchange/examples/ff/run.tcl b/fpga_interchange/examples/ff/run.tcl
deleted file mode 100644
index 726d86eb..00000000
--- a/fpga_interchange/examples/ff/run.tcl
+++ /dev/null
@@ -1,14 +0,0 @@
-yosys -import
-
-read_verilog ff.v
-
-synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json build/ff.json