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| author | gatecat <gatecat@ds0.me> | 2021-02-20 10:51:57 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-20 10:51:57 +0000 |
| commit | 6672f17d0a546054412c3ecad29a5414ffdcd971 (patch) | |
| tree | e0976dd397edf50fe89b5108751c5fb3a7ace896 /fpga_interchange/arch.cc | |
| parent | 130c5cc76882c2f07836b97040e6bc1d93e4efe9 (diff) | |
| parent | e571c707b50a601787590b9752205336ee1c3f6d (diff) | |
| download | nextpnr-6672f17d0a546054412c3ecad29a5414ffdcd971.tar.gz nextpnr-6672f17d0a546054412c3ecad29a5414ffdcd971.tar.bz2 nextpnr-6672f17d0a546054412c3ecad29a5414ffdcd971.zip | |
Merge pull request #592 from YosysHQ/gatecat/rework-delay
Replace DelayInfo with DelayPair and DelayQuad
Diffstat (limited to 'fpga_interchange/arch.cc')
| -rw-r--r-- | fpga_interchange/arch.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index 71ba46e4..9bcd7f79 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -686,7 +686,7 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const return 0; } -bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const +bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const { // FIXME: Implement when adding timing-driven place and route. return false; |