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author | David Shah <dave@ds0.me> | 2018-12-14 16:40:38 +0000 |
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committer | David Shah <dave@ds0.me> | 2018-12-14 16:40:38 +0000 |
commit | c01bb8850942ed690670ff5ded8eaaea0068e11e (patch) | |
tree | a49cdfe344d6a36478e82ca257feef6f26006593 /ecp5/arch.cc | |
parent | 9dc845b20d74031cd7bb4a520fc241d086befe77 (diff) | |
download | nextpnr-c01bb8850942ed690670ff5ded8eaaea0068e11e.tar.gz nextpnr-c01bb8850942ed690670ff5ded8eaaea0068e11e.tar.bz2 nextpnr-c01bb8850942ed690670ff5ded8eaaea0068e11e.zip |
ecp5: Add IOLOGIC timing and bitstream; ODDR working
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'ecp5/arch.cc')
-rw-r--r-- | ecp5/arch.cc | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 719426ab..380c0d7d 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -579,6 +579,8 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort return false; } else if (cell->type == id_DP16KD) { return false; + } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) { + return false; } else { return false; } @@ -669,6 +671,16 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT; } return TMG_IGNORE; + } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) { + if (port == id_CLK || port == id_ECLK) { + return TMG_CLOCK_INPUT; + } else if (port == id_IOLDO || port == id_IOLDOI || port == id_IOLDOD || port == id_IOLTO || port == id_PADDI || + port == id_DQSR90 || port == id_DQSW || port == id_DQSW270) { + return TMG_IGNORE; + } else { + clockInfoCount = 1; + return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT; + } } else { log_error("cell type '%s' is unsupported (instantiated as '%s')\n", cell->type.c_str(this), cell->name.c_str(this)); @@ -744,6 +756,14 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.setup = getDelayFromNS(1); info.hold = getDelayFromNS(0); } + } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) { + info.clock_port = id_CLK; + if (cell->ports.at(port).type == PORT_OUT) { + info.clockToQ = getDelayFromNS(0.5); + } else { + info.setup = getDelayFromNS(0.1); + info.hold = getDelayFromNS(0); + } } return info; } |