From 0adc0d75297fa81034aa3f325cf2758314ca1336 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 26 Nov 2018 18:56:10 +0000 Subject: timing: Improve clock constraint log output Signed-off-by: David Shah --- common/nextpnr.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/common/nextpnr.cc b/common/nextpnr.cc index be3bfe14..bb941d3d 100644 --- a/common/nextpnr.cc +++ b/common/nextpnr.cc @@ -409,12 +409,16 @@ void Context::check() const void BaseCtx::addClock(IdString net, float freq) { - log_info("constraining clock net '%s' to %.02f MHz\n", net.c_str(this), freq); std::unique_ptr cc(new ClockConstraint()); cc->period = getCtx()->getDelayFromNS(1000 / freq); cc->high = getCtx()->getDelayFromNS(500 / freq); cc->low = getCtx()->getDelayFromNS(500 / freq); - nets.at(net)->clkconstr = std::move(cc); + if (!nets.count(net)) { + log_warning("net '%s' does not exist in design, ignoring clock constraint\n", net.c_str(this)); + } else { + nets.at(net)->clkconstr = std::move(cc); + log_info("constraining clock net '%s' to %.02f MHz\n", net.c_str(this), freq); + } } NEXTPNR_NAMESPACE_END -- cgit v1.2.3