aboutsummaryrefslogtreecommitdiffstats
path: root/icebox/iceboxdb.py
Commit message (Expand)AuthorAgeFilesLines
* Remove seperate 5k RAM DB and share with 8k insteadDavid Shah2018-01-161-2838/+0
* Add missing 5k BRAM bitsDavid Shah2017-11-171-7/+338
* Trace DSP routingDavid Shah2017-11-171-324/+6374
* Add more 5k RAM bits to dbDavid Shah2017-11-051-4/+86
* Share glb_netwk data between 5k and 8k partsDavid Shah2017-10-291-72/+100
* Add ColBufCtrl bits to database for 5k partsDavid Shah2017-10-251-100/+72
* Swap IEREN for pin 26 to get example working, other inputs still need fixingDavid Shah2017-10-211-0/+71
* Modify icebox.py so it generates a 5k chipdbDavid Shah2017-10-201-30/+378
* Remove extra IoCtrl cf_bit_ and extra_padeb_test_ lines from databaseClifford Wolf2017-07-311-4/+0
* Work in progress DB. Having trouble getting group_segments to work without er...Scott Shawcroft2017-07-071-0/+2341
* icefuzz improvements, refuzz timingsClifford Wolf2016-01-161-0/+4
* Fuzzed RamCascade bitsClifford Wolf2016-01-091-0/+8
* Added lutff_i/lout net to modelClifford Wolf2015-12-041-7/+7
* Added 8k timing dataClifford Wolf2015-10-061-0/+1
* more database updatesClifford Wolf2015-10-021-0/+1
* database updatesClifford Wolf2015-09-271-0/+3
* Imported full dev sourcesClifford Wolf2015-07-181-138/+2902
* Import of icestorm-snapshot-150526.zipClifford Wolf2015-07-181-0/+9
* Import of icestorm-snapshot-150413.zipClifford Wolf2015-07-181-73/+2496
* Import of icestorm-snapshot-150322.zipClifford Wolf2015-07-181-0/+2985
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 03:33:31 +0000