diff options
author | Clifford Wolf <clifford@clifford.at> | 2015-07-18 13:05:02 +0200 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2015-07-18 13:05:02 +0200 |
commit | dfeb92a46b2228b4f3886a9c06502ccd0dde5562 (patch) | |
tree | 20cebe482ae2954f4597489658b27828f5316921 /icebox/iceboxdb.py | |
download | icestorm-dfeb92a46b2228b4f3886a9c06502ccd0dde5562.tar.gz icestorm-dfeb92a46b2228b4f3886a9c06502ccd0dde5562.tar.bz2 icestorm-dfeb92a46b2228b4f3886a9c06502ccd0dde5562.zip |
Import of icestorm-snapshot-150322.zip
Diffstat (limited to 'icebox/iceboxdb.py')
-rw-r--r-- | icebox/iceboxdb.py | 2985 |
1 files changed, 2985 insertions, 0 deletions
diff --git a/icebox/iceboxdb.py b/icebox/iceboxdb.py new file mode 100644 index 0000000..dd4e0c7 --- /dev/null +++ b/icebox/iceboxdb.py @@ -0,0 +1,2985 @@ +database_io_txt = """ +B1[9] ColBufCtrl IO_half_column_clock_enable_0 B1[9] +B0[9] ColBufCtrl IO_half_column_clock_enable_1 B0[9] +B3[9] ColBufCtrl IO_half_column_clock_enable_2 B3[9] +B2[9] ColBufCtrl IO_half_column_clock_enable_3 B2[9] +B5[9] ColBufCtrl IO_half_column_clock_enable_4 B5[9] +B4[9] ColBufCtrl IO_half_column_clock_enable_5 B4[9] +B7[9] ColBufCtrl IO_half_column_clock_enable_6 B7[9] +B6[9] ColBufCtrl IO_half_column_clock_enable_7 B6[9] +B3[17] IOB_0 PINTYPE_0 +B3[16] IOB_0 PINTYPE_1 +B0[17] IOB_0 PINTYPE_2 +B0[16] IOB_0 PINTYPE_3 +B4[16] IOB_0 PINTYPE_4 +B4[17] IOB_0 PINTYPE_5 +B13[17] IOB_1 PINTYPE_0 +B13[16] IOB_1 PINTYPE_1 +B10[17] IOB_1 PINTYPE_2 +B10[16] IOB_1 PINTYPE_3 +B14[16] IOB_1 PINTYPE_4 +B14[17] IOB_1 PINTYPE_5 +B9[3] IoCtrl IE_0 +B6[3] IoCtrl IE_1 +B6[2] IoCtrl REN_0 +B1[3] IoCtrl REN_1 +B9[13],B15[13] NegClk +B0[4],!B1[4],!B1[5],!B1[6],B1[7] buffer IO_B.logic_op_tnl_0 lc_trk_g0_0 +B8[4],!B9[4],!B9[5],!B9[6],B9[7] buffer IO_B.logic_op_tnl_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer IO_B.logic_op_tnl_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer IO_B.logic_op_tnl_1 lc_trk_g1_1 +B2[4],!B3[4],!B3[5],!B3[6],B3[7] buffer IO_B.logic_op_tnl_2 lc_trk_g0_2 +B10[4],!B11[4],!B11[5],!B11[6],B11[7] buffer IO_B.logic_op_tnl_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer IO_B.logic_op_tnl_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer IO_B.logic_op_tnl_3 lc_trk_g1_3 +B4[4],!B5[4],!B5[5],!B5[6],B5[7] buffer IO_B.logic_op_tnl_4 lc_trk_g0_4 +B12[4],!B13[4],!B13[5],!B13[6],B13[7] buffer IO_B.logic_op_tnl_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer IO_B.logic_op_tnl_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer IO_B.logic_op_tnl_5 lc_trk_g1_5 +B6[4],!B7[4],!B7[5],!B7[6],B7[7] buffer IO_B.logic_op_tnl_6 lc_trk_g0_6 +B14[4],!B15[4],!B15[5],!B15[6],B15[7] buffer IO_B.logic_op_tnl_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer IO_B.logic_op_tnl_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer IO_B.logic_op_tnl_7 lc_trk_g1_7 +!B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer IO_B.logic_op_tnr_0 lc_trk_g0_0 +!B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer IO_B.logic_op_tnr_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],!B0[8],!B1[8] buffer IO_B.logic_op_tnr_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],!B8[8],!B9[8] buffer IO_B.logic_op_tnr_1 lc_trk_g1_1 +!B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer IO_B.logic_op_tnr_2 lc_trk_g0_2 +!B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer IO_B.logic_op_tnr_2 lc_trk_g1_2 +B2[5],!B2[6],B2[7],!B2[8],!B3[8] buffer IO_B.logic_op_tnr_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],!B10[8],!B11[8] buffer IO_B.logic_op_tnr_3 lc_trk_g1_3 +!B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer IO_B.logic_op_tnr_4 lc_trk_g0_4 +!B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer IO_B.logic_op_tnr_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],!B4[8],!B5[8] buffer IO_B.logic_op_tnr_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],!B12[8],!B13[8] buffer IO_B.logic_op_tnr_5 lc_trk_g1_5 +!B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer IO_B.logic_op_tnr_6 lc_trk_g0_6 +!B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer IO_B.logic_op_tnr_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],!B6[8],!B7[8] buffer IO_B.logic_op_tnr_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],!B14[8],!B15[8] buffer IO_B.logic_op_tnr_7 lc_trk_g1_7 +B0[4],B1[4],!B1[5],!B1[6],B1[7] buffer IO_B.logic_op_top_0 lc_trk_g0_0 +B8[4],B9[4],!B9[5],!B9[6],B9[7] buffer IO_B.logic_op_top_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],B1[8] buffer IO_B.logic_op_top_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],B9[8] buffer IO_B.logic_op_top_1 lc_trk_g1_1 +B2[4],B3[4],!B3[5],!B3[6],B3[7] buffer IO_B.logic_op_top_2 lc_trk_g0_2 +B10[4],B11[4],!B11[5],!B11[6],B11[7] buffer IO_B.logic_op_top_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],B3[8] buffer IO_B.logic_op_top_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],B11[8] buffer IO_B.logic_op_top_3 lc_trk_g1_3 +B4[4],B5[4],!B5[5],!B5[6],B5[7] buffer IO_B.logic_op_top_4 lc_trk_g0_4 +B12[4],B13[4],!B13[5],!B13[6],B13[7] buffer IO_B.logic_op_top_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],B5[8] buffer IO_B.logic_op_top_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],B13[8] buffer IO_B.logic_op_top_5 lc_trk_g1_5 +B6[4],B7[4],!B7[5],!B7[6],B7[7] buffer IO_B.logic_op_top_6 lc_trk_g0_6 +B14[4],B15[4],!B15[5],!B15[6],B15[7] buffer IO_B.logic_op_top_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],B7[8] buffer IO_B.logic_op_top_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],B15[8] buffer IO_B.logic_op_top_7 lc_trk_g1_7 +!B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer IO_L.logic_op_bnr_0 lc_trk_g0_0 +!B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer IO_L.logic_op_bnr_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],!B0[8],!B1[8] buffer IO_L.logic_op_bnr_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],!B8[8],!B9[8] buffer IO_L.logic_op_bnr_1 lc_trk_g1_1 +!B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer IO_L.logic_op_bnr_2 lc_trk_g0_2 +!B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer IO_L.logic_op_bnr_2 lc_trk_g1_2 +B2[5],!B2[6],B2[7],!B2[8],!B3[8] buffer IO_L.logic_op_bnr_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],!B10[8],!B11[8] buffer IO_L.logic_op_bnr_3 lc_trk_g1_3 +!B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer IO_L.logic_op_bnr_4 lc_trk_g0_4 +!B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer IO_L.logic_op_bnr_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],!B4[8],!B5[8] buffer IO_L.logic_op_bnr_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],!B12[8],!B13[8] buffer IO_L.logic_op_bnr_5 lc_trk_g1_5 +!B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer IO_L.logic_op_bnr_6 lc_trk_g0_6 +!B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer IO_L.logic_op_bnr_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],!B6[8],!B7[8] buffer IO_L.logic_op_bnr_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],!B14[8],!B15[8] buffer IO_L.logic_op_bnr_7 lc_trk_g1_7 +B0[4],B1[4],!B1[5],!B1[6],B1[7] buffer IO_L.logic_op_rgt_0 lc_trk_g0_0 +B8[4],B9[4],!B9[5],!B9[6],B9[7] buffer IO_L.logic_op_rgt_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],B1[8] buffer IO_L.logic_op_rgt_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],B9[8] buffer IO_L.logic_op_rgt_1 lc_trk_g1_1 +B2[4],B3[4],!B3[5],!B3[6],B3[7] buffer IO_L.logic_op_rgt_2 lc_trk_g0_2 +B10[4],B11[4],!B11[5],!B11[6],B11[7] buffer IO_L.logic_op_rgt_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],B3[8] buffer IO_L.logic_op_rgt_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],B11[8] buffer IO_L.logic_op_rgt_3 lc_trk_g1_3 +B4[4],B5[4],!B5[5],!B5[6],B5[7] buffer IO_L.logic_op_rgt_4 lc_trk_g0_4 +B12[4],B13[4],!B13[5],!B13[6],B13[7] buffer IO_L.logic_op_rgt_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],B5[8] buffer IO_L.logic_op_rgt_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],B13[8] buffer IO_L.logic_op_rgt_5 lc_trk_g1_5 +B6[4],B7[4],!B7[5],!B7[6],B7[7] buffer IO_L.logic_op_rgt_6 lc_trk_g0_6 +B14[4],B15[4],!B15[5],!B15[6],B15[7] buffer IO_L.logic_op_rgt_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],B7[8] buffer IO_L.logic_op_rgt_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],B15[8] buffer IO_L.logic_op_rgt_7 lc_trk_g1_7 +B0[4],!B1[4],!B1[5],!B1[6],B1[7] buffer IO_L.logic_op_tnr_0 lc_trk_g0_0 +B8[4],!B9[4],!B9[5],!B9[6],B9[7] buffer IO_L.logic_op_tnr_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer IO_L.logic_op_tnr_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer IO_L.logic_op_tnr_1 lc_trk_g1_1 +B2[4],!B3[4],!B3[5],!B3[6],B3[7] buffer IO_L.logic_op_tnr_2 lc_trk_g0_2 +B10[4],!B11[4],!B11[5],!B11[6],B11[7] buffer IO_L.logic_op_tnr_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer IO_L.logic_op_tnr_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer IO_L.logic_op_tnr_3 lc_trk_g1_3 +B4[4],!B5[4],!B5[5],!B5[6],B5[7] buffer IO_L.logic_op_tnr_4 lc_trk_g0_4 +B12[4],!B13[4],!B13[5],!B13[6],B13[7] buffer IO_L.logic_op_tnr_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer IO_L.logic_op_tnr_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer IO_L.logic_op_tnr_5 lc_trk_g1_5 +B6[4],!B7[4],!B7[5],!B7[6],B7[7] buffer IO_L.logic_op_tnr_6 lc_trk_g0_6 +B14[4],!B15[4],!B15[5],!B15[6],B15[7] buffer IO_L.logic_op_tnr_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer IO_L.logic_op_tnr_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer IO_L.logic_op_tnr_7 lc_trk_g1_7 +!B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer IO_R.logic_op_bnl_0 lc_trk_g0_0 +!B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer IO_R.logic_op_bnl_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],!B0[8],!B1[8] buffer IO_R.logic_op_bnl_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],!B8[8],!B9[8] buffer IO_R.logic_op_bnl_1 lc_trk_g1_1 +!B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer IO_R.logic_op_bnl_2 lc_trk_g0_2 +!B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer IO_R.logic_op_bnl_2 lc_trk_g1_2 +B2[5],!B2[6],B2[7],!B2[8],!B3[8] buffer IO_R.logic_op_bnl_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],!B10[8],!B11[8] buffer IO_R.logic_op_bnl_3 lc_trk_g1_3 +!B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer IO_R.logic_op_bnl_4 lc_trk_g0_4 +!B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer IO_R.logic_op_bnl_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],!B4[8],!B5[8] buffer IO_R.logic_op_bnl_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],!B12[8],!B13[8] buffer IO_R.logic_op_bnl_5 lc_trk_g1_5 +!B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer IO_R.logic_op_bnl_6 lc_trk_g0_6 +!B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer IO_R.logic_op_bnl_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],!B6[8],!B7[8] buffer IO_R.logic_op_bnl_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],!B14[8],!B15[8] buffer IO_R.logic_op_bnl_7 lc_trk_g1_7 +B0[4],B1[4],!B1[5],!B1[6],B1[7] buffer IO_R.logic_op_lft_0 lc_trk_g0_0 +B8[4],B9[4],!B9[5],!B9[6],B9[7] buffer IO_R.logic_op_lft_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],B1[8] buffer IO_R.logic_op_lft_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],B9[8] buffer IO_R.logic_op_lft_1 lc_trk_g1_1 +B2[4],B3[4],!B3[5],!B3[6],B3[7] buffer IO_R.logic_op_lft_2 lc_trk_g0_2 +B10[4],B11[4],!B11[5],!B11[6],B11[7] buffer IO_R.logic_op_lft_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],B3[8] buffer IO_R.logic_op_lft_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],B11[8] buffer IO_R.logic_op_lft_3 lc_trk_g1_3 +B4[4],B5[4],!B5[5],!B5[6],B5[7] buffer IO_R.logic_op_lft_4 lc_trk_g0_4 +B12[4],B13[4],!B13[5],!B13[6],B13[7] buffer IO_R.logic_op_lft_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],B5[8] buffer IO_R.logic_op_lft_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],B13[8] buffer IO_R.logic_op_lft_5 lc_trk_g1_5 +B6[4],B7[4],!B7[5],!B7[6],B7[7] buffer IO_R.logic_op_lft_6 lc_trk_g0_6 +B14[4],B15[4],!B15[5],!B15[6],B15[7] buffer IO_R.logic_op_lft_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],B7[8] buffer IO_R.logic_op_lft_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],B15[8] buffer IO_R.logic_op_lft_7 lc_trk_g1_7 +B0[4],!B1[4],!B1[5],!B1[6],B1[7] buffer IO_R.logic_op_tnl_0 lc_trk_g0_0 +B8[4],!B9[4],!B9[5],!B9[6],B9[7] buffer IO_R.logic_op_tnl_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer IO_R.logic_op_tnl_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer IO_R.logic_op_tnl_1 lc_trk_g1_1 +B2[4],!B3[4],!B3[5],!B3[6],B3[7] buffer IO_R.logic_op_tnl_2 lc_trk_g0_2 +B10[4],!B11[4],!B11[5],!B11[6],B11[7] buffer IO_R.logic_op_tnl_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer IO_R.logic_op_tnl_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer IO_R.logic_op_tnl_3 lc_trk_g1_3 +B4[4],!B5[4],!B5[5],!B5[6],B5[7] buffer IO_R.logic_op_tnl_4 lc_trk_g0_4 +B12[4],!B13[4],!B13[5],!B13[6],B13[7] buffer IO_R.logic_op_tnl_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer IO_R.logic_op_tnl_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer IO_R.logic_op_tnl_5 lc_trk_g1_5 +B6[4],!B7[4],!B7[5],!B7[6],B7[7] buffer IO_R.logic_op_tnl_6 lc_trk_g0_6 +B14[4],!B15[4],!B15[5],!B15[6],B15[7] buffer IO_R.logic_op_tnl_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer IO_R.logic_op_tnl_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer IO_R.logic_op_tnl_7 lc_trk_g1_7 +B0[4],!B1[4],!B1[5],!B1[6],B1[7] buffer IO_T.logic_op_bnl_0 lc_trk_g0_0 +B8[4],!B9[4],!B9[5],!B9[6],B9[7] buffer IO_T.logic_op_bnl_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer IO_T.logic_op_bnl_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer IO_T.logic_op_bnl_1 lc_trk_g1_1 +B2[4],!B3[4],!B3[5],!B3[6],B3[7] buffer IO_T.logic_op_bnl_2 lc_trk_g0_2 +B10[4],!B11[4],!B11[5],!B11[6],B11[7] buffer IO_T.logic_op_bnl_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer IO_T.logic_op_bnl_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer IO_T.logic_op_bnl_3 lc_trk_g1_3 +B4[4],!B5[4],!B5[5],!B5[6],B5[7] buffer IO_T.logic_op_bnl_4 lc_trk_g0_4 +B12[4],!B13[4],!B13[5],!B13[6],B13[7] buffer IO_T.logic_op_bnl_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer IO_T.logic_op_bnl_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer IO_T.logic_op_bnl_5 lc_trk_g1_5 +B6[4],!B7[4],!B7[5],!B7[6],B7[7] buffer IO_T.logic_op_bnl_6 lc_trk_g0_6 +B14[4],!B15[4],!B15[5],!B15[6],B15[7] buffer IO_T.logic_op_bnl_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer IO_T.logic_op_bnl_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer IO_T.logic_op_bnl_7 lc_trk_g1_7 +!B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer IO_T.logic_op_bnr_0 lc_trk_g0_0 +!B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer IO_T.logic_op_bnr_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],!B0[8],!B1[8] buffer IO_T.logic_op_bnr_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],!B8[8],!B9[8] buffer IO_T.logic_op_bnr_1 lc_trk_g1_1 +!B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer IO_T.logic_op_bnr_2 lc_trk_g0_2 +!B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer IO_T.logic_op_bnr_2 lc_trk_g1_2 +B2[5],!B2[6],B2[7],!B2[8],!B3[8] buffer IO_T.logic_op_bnr_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],!B10[8],!B11[8] buffer IO_T.logic_op_bnr_3 lc_trk_g1_3 +!B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer IO_T.logic_op_bnr_4 lc_trk_g0_4 +!B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer IO_T.logic_op_bnr_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],!B4[8],!B5[8] buffer IO_T.logic_op_bnr_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],!B12[8],!B13[8] buffer IO_T.logic_op_bnr_5 lc_trk_g1_5 +!B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer IO_T.logic_op_bnr_6 lc_trk_g0_6 +!B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer IO_T.logic_op_bnr_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],!B6[8],!B7[8] buffer IO_T.logic_op_bnr_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],!B14[8],!B15[8] buffer IO_T.logic_op_bnr_7 lc_trk_g1_7 +B0[4],B1[4],!B1[5],!B1[6],B1[7] buffer IO_T.logic_op_bot_0 lc_trk_g0_0 +B8[4],B9[4],!B9[5],!B9[6],B9[7] buffer IO_T.logic_op_bot_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],B1[8] buffer IO_T.logic_op_bot_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],B9[8] buffer IO_T.logic_op_bot_1 lc_trk_g1_1 +B2[4],B3[4],!B3[5],!B3[6],B3[7] buffer IO_T.logic_op_bot_2 lc_trk_g0_2 +B10[4],B11[4],!B11[5],!B11[6],B11[7] buffer IO_T.logic_op_bot_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],B3[8] buffer IO_T.logic_op_bot_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],B11[8] buffer IO_T.logic_op_bot_3 lc_trk_g1_3 +B4[4],B5[4],!B5[5],!B5[6],B5[7] buffer IO_T.logic_op_bot_4 lc_trk_g0_4 +B12[4],B13[4],!B13[5],!B13[6],B13[7] buffer IO_T.logic_op_bot_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],B5[8] buffer IO_T.logic_op_bot_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],B13[8] buffer IO_T.logic_op_bot_5 lc_trk_g1_5 +B6[4],B7[4],!B7[5],!B7[6],B7[7] buffer IO_T.logic_op_bot_6 lc_trk_g0_6 +B14[4],B15[4],!B15[5],!B15[6],B15[7] buffer IO_T.logic_op_bot_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],B7[8] buffer IO_T.logic_op_bot_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],B15[8] buffer IO_T.logic_op_bot_7 lc_trk_g1_7 +!B8[12],!B8[13],!B8[14],!B9[12],B9[15] buffer glb_netwk_0 wire_io_cluster/io_1/inclk +!B14[12],!B14[13],!B14[14],!B15[12],B15[15] buffer glb_netwk_0 wire_io_cluster/io_1/outclk +!B8[12],!B8[13],!B8[14],B9[12],B9[15] buffer glb_netwk_1 wire_io_cluster/io_1/inclk +!B14[12],!B14[13],!B14[14],B15[12],B15[15] buffer glb_netwk_1 wire_io_cluster/io_1/outclk +B8[12],!B8[13],!B8[14],!B9[12],B9[15] buffer glb_netwk_2 wire_io_cluster/io_1/inclk +B14[12],!B14[13],!B14[14],!B15[12],B15[15] buffer glb_netwk_2 wire_io_cluster/io_1/outclk +B8[12],!B8[13],!B8[14],B9[12],B9[15] buffer glb_netwk_3 wire_io_cluster/io_1/inclk +B14[12],!B14[13],!B14[14],B15[12],B15[15] buffer glb_netwk_3 wire_io_cluster/io_1/outclk +!B8[12],!B8[13],B8[14],!B9[12],B9[15] buffer glb_netwk_4 wire_io_cluster/io_1/inclk +!B14[12],!B14[13],B14[14],!B15[12],B15[15] buffer glb_netwk_4 wire_io_cluster/io_1/outclk +!B8[12],!B8[13],B8[14],B9[12],B9[15] buffer glb_netwk_5 wire_io_cluster/io_1/inclk +!B14[12],!B14[13],B14[14],B15[12],B15[15] buffer glb_netwk_5 wire_io_cluster/io_1/outclk +B8[12],!B8[13],B8[14],!B9[12],B9[15] buffer glb_netwk_6 wire_io_cluster/io_1/inclk +B14[12],!B14[13],B14[14],!B15[12],B15[15] buffer glb_netwk_6 wire_io_cluster/io_1/outclk +B8[12],!B8[13],B8[14],B9[12],B9[15] buffer glb_netwk_7 wire_io_cluster/io_1/inclk +B14[12],!B14[13],B14[14],B15[12],B15[15] buffer glb_netwk_7 wire_io_cluster/io_1/outclk +!B4[12],!B4[13],!B5[12],B5[13] buffer lc_trk_g0_0 wire_io_cluster/io_0/D_OUT_0 +!B14[10],!B14[11],!B15[10],B15[11] buffer lc_trk_g0_0 wire_io_cluster/io_1/D_OUT_1 +!B10[10],!B10[11],!B11[10],B11[11] buffer lc_trk_g0_0 wire_io_cluster/io_1/OUT_ENB +!B8[12],B8[13],!B8[14],!B9[12],B9[15] buffer lc_trk_g0_0 wire_io_cluster/io_1/inclk +!B4[14],B4[15],!B5[14],!B5[15] buffer lc_trk_g0_1 wire_gbuf/in +!B8[10],!B8[11],!B9[10],B9[11] buffer lc_trk_g0_1 wire_io_cluster/io_0/D_OUT_1 +!B4[10],!B4[11],!B5[10],B5[11] buffer lc_trk_g0_1 wire_io_cluster/io_0/OUT_ENB +!B10[12],!B10[13],!B11[12],B11[13] buffer lc_trk_g0_1 wire_io_cluster/io_1/D_OUT_0 +!B14[12],B14[13],!B14[14],!B15[12],B15[15] buffer lc_trk_g0_1 wire_io_cluster/io_1/outclk +!B4[12],!B4[13],B5[12],B5[13] buffer lc_trk_g0_2 wire_io_cluster/io_0/D_OUT_0 +!B14[10],!B14[11],B15[10],B15[11] buffer lc_trk_g0_2 wire_io_cluster/io_1/D_OUT_1 +!B10[10],!B10[11],B11[10],B11[11] buffer lc_trk_g0_2 wire_io_cluster/io_1/OUT_ENB +!B10[14],B10[15],B11[14],!B11[15] buffer lc_trk_g0_2 wire_io_cluster/io_1/cen +B4[14],B4[15],!B5[14],!B5[15] buffer lc_trk_g0_3 wire_gbuf/in +!B8[10],!B8[11],B9[10],B9[11] buffer lc_trk_g0_3 wire_io_cluster/io_0/D_OUT_1 +!B4[10],!B4[11],B5[10],B5[11] buffer lc_trk_g0_3 wire_io_cluster/io_0/OUT_ENB +!B10[12],!B10[13],B11[12],B11[13] buffer lc_trk_g0_3 wire_io_cluster/io_1/D_OUT_0 +!B8[12],B8[13],!B8[14],B9[12],B9[15] buffer lc_trk_g0_3 wire_io_cluster/io_1/inclk +!B4[12],B4[13],!B5[12],B5[13] buffer lc_trk_g0_4 wire_io_cluster/io_0/D_OUT_0 +B14[10],!B14[11],!B15[10],B15[11] buffer lc_trk_g0_4 wire_io_cluster/io_1/D_OUT_1 +B10[10],!B10[11],!B11[10],B11[11] buffer lc_trk_g0_4 wire_io_cluster/io_1/OUT_ENB +!B14[12],B14[13],!B14[14],B15[12],B15[15] buffer lc_trk_g0_4 wire_io_cluster/io_1/outclk +!B4[14],B4[15],!B5[14],B5[15] buffer lc_trk_g0_5 wire_gbuf/in +B8[10],!B8[11],!B9[10],B9[11] buffer lc_trk_g0_5 wire_io_cluster/io_0/D_OUT_1 +B4[10],!B4[11],!B5[10],B5[11] buffer lc_trk_g0_5 wire_io_cluster/io_0/OUT_ENB +!B10[12],B10[13],!B11[12],B11[13] buffer lc_trk_g0_5 wire_io_cluster/io_1/D_OUT_0 +B10[14],B10[15],B11[14],!B11[15] buffer lc_trk_g0_5 wire_io_cluster/io_1/cen +!B4[12],B4[13],B5[12],B5[13] buffer lc_trk_g0_6 wire_io_cluster/io_0/D_OUT_0 +B14[10],!B14[11],B15[10],B15[11] buffer lc_trk_g0_6 wire_io_cluster/io_1/D_OUT_1 +B10[10],!B10[11],B11[10],B11[11] buffer lc_trk_g0_6 wire_io_cluster/io_1/OUT_ENB +B4[14],B4[15],!B5[14],B5[15] buffer lc_trk_g0_7 wire_gbuf/in +B8[10],!B8[11],B9[10],B9[11] buffer lc_trk_g0_7 wire_io_cluster/io_0/D_OUT_1 +B4[10],!B4[11],B5[10],B5[11] buffer lc_trk_g0_7 wire_io_cluster/io_0/OUT_ENB +!B10[12],B10[13],B11[12],B11[13] buffer lc_trk_g0_7 wire_io_cluster/io_1/D_OUT_0 +!B4[14],B4[15],B5[14],!B5[15] buffer lc_trk_g1_0 wire_gbuf/in +!B8[10],B8[11],!B9[10],B9[11] buffer lc_trk_g1_0 wire_io_cluster/io_0/D_OUT_1 +!B4[10],B4[11],!B5[10],B5[11] buffer lc_trk_g1_0 wire_io_cluster/io_0/OUT_ENB +B10[12],!B10[13],!B11[12],B11[13] buffer lc_trk_g1_0 wire_io_cluster/io_1/D_OUT_0 +B8[12],B8[13],!B8[14],!B9[12],B9[15] buffer lc_trk_g1_0 wire_io_cluster/io_1/inclk +B4[12],!B4[13],!B5[12],B5[13] buffer lc_trk_g1_1 wire_io_cluster/io_0/D_OUT_0 +!B14[10],B14[11],!B15[10],B15[11] buffer lc_trk_g1_1 wire_io_cluster/io_1/D_OUT_1 +!B10[10],B10[11],!B11[10],B11[11] buffer lc_trk_g1_1 wire_io_cluster/io_1/OUT_ENB +B14[12],B14[13],!B14[14],!B15[12],B15[15] buffer lc_trk_g1_1 wire_io_cluster/io_1/outclk +B4[14],B4[15],B5[14],!B5[15] buffer lc_trk_g1_2 wire_gbuf/in +!B8[10],B8[11],B9[10],B9[11] buffer lc_trk_g1_2 wire_io_cluster/io_0/D_OUT_1 +!B4[10],B4[11],B5[10],B5[11] buffer lc_trk_g1_2 wire_io_cluster/io_0/OUT_ENB +B10[12],!B10[13],B11[12],B11[13] buffer lc_trk_g1_2 wire_io_cluster/io_1/D_OUT_0 +!B10[14],B10[15],B11[14],B11[15] buffer lc_trk_g1_2 wire_io_cluster/io_1/cen +B4[12],!B4[13],B5[12],B5[13] buffer lc_trk_g1_3 wire_io_cluster/io_0/D_OUT_0 +!B14[10],B14[11],B15[10],B15[11] buffer lc_trk_g1_3 wire_io_cluster/io_1/D_OUT_1 +!B10[10],B10[11],B11[10],B11[11] buffer lc_trk_g1_3 wire_io_cluster/io_1/OUT_ENB +B8[12],B8[13],!B8[14],B9[12],B9[15] buffer lc_trk_g1_3 wire_io_cluster/io_1/inclk +!B4[14],B4[15],B5[14],B5[15] buffer lc_trk_g1_4 wire_gbuf/in +B8[10],B8[11],!B9[10],B9[11] buffer lc_trk_g1_4 wire_io_cluster/io_0/D_OUT_1 +B4[10],B4[11],!B5[10],B5[11] buffer lc_trk_g1_4 wire_io_cluster/io_0/OUT_ENB +B10[12],B10[13],!B11[12],B11[13] buffer lc_trk_g1_4 wire_io_cluster/io_1/D_OUT_0 +B14[12],B14[13],!B14[14],B15[12],B15[15] buffer lc_trk_g1_4 wire_io_cluster/io_1/outclk +B4[12],B4[13],!B5[12],B5[13] buffer lc_trk_g1_5 wire_io_cluster/io_0/D_OUT_0 +B14[10],B14[11],!B15[10],B15[11] buffer lc_trk_g1_5 wire_io_cluster/io_1/D_OUT_1 +B10[10],B10[11],!B11[10],B11[11] buffer lc_trk_g1_5 wire_io_cluster/io_1/OUT_ENB +B10[14],B10[15],B11[14],B11[15] buffer lc_trk_g1_5 wire_io_cluster/io_1/cen +B4[14],B4[15],B5[14],B5[15] buffer lc_trk_g1_6 wire_gbuf/in +B8[10],B8[11],B9[10],B9[11] buffer lc_trk_g1_6 wire_io_cluster/io_0/D_OUT_1 +B4[10],B4[11],B5[10],B5[11] buffer lc_trk_g1_6 wire_io_cluster/io_0/OUT_ENB +B10[12],B10[13],B11[12],B11[13] buffer lc_trk_g1_6 wire_io_cluster/io_1/D_OUT_0 +B4[12],B4[13],B5[12],B5[13] buffer lc_trk_g1_7 wire_io_cluster/io_0/D_OUT_0 +B14[10],B14[11],B15[10],B15[11] buffer lc_trk_g1_7 wire_io_cluster/io_1/D_OUT_1 +B10[10],B10[11],B11[10],B11[11] buffer lc_trk_g1_7 wire_io_cluster/io_1/OUT_ENB +B0[4],B1[4],B1[5],!B1[6],B1[7] buffer span12_horz_0 lc_trk_g0_0 +B8[4],B9[4],B9[5],!B9[6],B9[7] buffer span12_horz_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],B0[8],B1[8] buffer span12_horz_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],B8[8],B9[8] buffer span12_horz_1 lc_trk_g1_1 +!B2[4],!B3[4],!B3[5],B3[6],B3[7] buffer span12_horz_10 lc_trk_g0_2 +!B10[4],!B11[4],!B11[5],B11[6],B11[7] buffer span12_horz_10 lc_trk_g1_2 +!B2[5],B2[6],B2[7],!B2[8],!B3[8] buffer span12_horz_11 lc_trk_g0_3 +!B10[5],B10[6],B10[7],!B10[8],!B11[8] buffer span12_horz_11 lc_trk_g1_3 +!B4[4],!B5[4],!B5[5],B5[6],B5[7] buffer span12_horz_12 lc_trk_g0_4 +!B12[4],!B13[4],!B13[5],B13[6],B13[7] buffer span12_horz_12 lc_trk_g1_4 +!B4[5],B4[6],B4[7],!B4[8],!B5[8] buffer span12_horz_13 lc_trk_g0_5 +!B12[5],B12[6],B12[7],!B12[8],!B13[8] buffer span12_horz_13 lc_trk_g1_5 +!B6[4],!B7[4],!B7[5],B7[6],B7[7] buffer span12_horz_14 lc_trk_g0_6 +!B14[4],!B15[4],!B15[5],B15[6],B15[7] buffer span12_horz_14 lc_trk_g1_6 +!B6[5],B6[6],B6[7],!B6[8],!B7[8] buffer span12_horz_15 lc_trk_g0_7 +!B14[5],B14[6],B14[7],!B14[8],!B15[8] buffer span12_horz_15 lc_trk_g1_7 +!B0[4],B1[4],!B1[5],B1[6],B1[7] buffer span12_horz_16 lc_trk_g0_0 +!B8[4],B9[4],!B9[5],B9[6],B9[7] buffer span12_horz_16 lc_trk_g1_0 +!B0[5],B0[6],B0[7],!B0[8],B1[8] buffer span12_horz_17 lc_trk_g0_1 +!B8[5],B8[6],B8[7],!B8[8],B9[8] buffer span12_horz_17 lc_trk_g1_1 +!B2[4],B3[4],!B3[5],B3[6],B3[7] buffer span12_horz_18 lc_trk_g0_2 +!B10[4],B11[4],!B11[5],B11[6],B11[7] buffer span12_horz_18 lc_trk_g1_2 +!B2[5],B2[6],B2[7],!B2[8],B3[8] buffer span12_horz_19 lc_trk_g0_3 +!B10[5],B10[6],B10[7],!B10[8],B11[8] buffer span12_horz_19 lc_trk_g1_3 +B2[4],B3[4],B3[5],!B3[6],B3[7] buffer span12_horz_2 lc_trk_g0_2 +B10[4],B11[4],B11[5],!B11[6],B11[7] buffer span12_horz_2 lc_trk_g1_2 +!B4[4],B5[4],!B5[5],B5[6],B5[7] buffer span12_horz_20 lc_trk_g0_4 +!B12[4],B13[4],!B13[5],B13[6],B13[7] buffer span12_horz_20 lc_trk_g1_4 +!B4[5],B4[6],B4[7],!B4[8],B5[8] buffer span12_horz_21 lc_trk_g0_5 +!B12[5],B12[6],B12[7],!B12[8],B13[8] buffer span12_horz_21 lc_trk_g1_5 +!B6[4],B7[4],!B7[5],B7[6],B7[7] buffer span12_horz_22 lc_trk_g0_6 +!B14[4],B15[4],!B15[5],B15[6],B15[7] buffer span12_horz_22 lc_trk_g1_6 +!B6[5],B6[6],B6[7],!B6[8],B7[8] buffer span12_horz_23 lc_trk_g0_7 +!B14[5],B14[6],B14[7],!B14[8],B15[8] buffer span12_horz_23 lc_trk_g1_7 +B2[5],!B2[6],B2[7],B2[8],B3[8] buffer span12_horz_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],B10[8],B11[8] buffer span12_horz_3 lc_trk_g1_3 +B4[4],B5[4],B5[5],!B5[6],B5[7] buffer span12_horz_4 lc_trk_g0_4 +B12[4],B13[4],B13[5],!B13[6],B13[7] buffer span12_horz_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],B4[8],B5[8] buffer span12_horz_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],B12[8],B13[8] buffer span12_horz_5 lc_trk_g1_5 +B6[4],B7[4],B7[5],!B7[6],B7[7] buffer span12_horz_6 lc_trk_g0_6 +B14[4],B15[4],B15[5],!B15[6],B15[7] buffer span12_horz_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],B6[8],B7[8] buffer span12_horz_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],B14[8],B15[8] buffer span12_horz_7 lc_trk_g1_7 +!B0[4],!B1[4],!B1[5],B1[6],B1[7] buffer span12_horz_8 lc_trk_g0_0 +!B8[4],!B9[4],!B9[5],B9[6],B9[7] buffer span12_horz_8 lc_trk_g1_0 +!B0[5],B0[6],B0[7],!B0[8],!B1[8] buffer span12_horz_9 lc_trk_g0_1 +!B8[5],B8[6],B8[7],!B8[8],!B9[8] buffer span12_horz_9 lc_trk_g1_1 +B0[4],B1[4],B1[5],!B1[6],B1[7] buffer span12_vert_0 lc_trk_g0_0 +B8[4],B9[4],B9[5],!B9[6],B9[7] buffer span12_vert_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],B0[8],B1[8] buffer span12_vert_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],B8[8],B9[8] buffer span12_vert_1 lc_trk_g1_1 +!B2[4],!B3[4],!B3[5],B3[6],B3[7] buffer span12_vert_10 lc_trk_g0_2 +!B10[4],!B11[4],!B11[5],B11[6],B11[7] buffer span12_vert_10 lc_trk_g1_2 +!B2[5],B2[6],B2[7],!B2[8],!B3[8] buffer span12_vert_11 lc_trk_g0_3 +!B10[5],B10[6],B10[7],!B10[8],!B11[8] buffer span12_vert_11 lc_trk_g1_3 +!B4[4],!B5[4],!B5[5],B5[6],B5[7] buffer span12_vert_12 lc_trk_g0_4 +!B12[4],!B13[4],!B13[5],B13[6],B13[7] buffer span12_vert_12 lc_trk_g1_4 +!B4[5],B4[6],B4[7],!B4[8],!B5[8] buffer span12_vert_13 lc_trk_g0_5 +!B12[5],B12[6],B12[7],!B12[8],!B13[8] buffer span12_vert_13 lc_trk_g1_5 +!B6[4],!B7[4],!B7[5],B7[6],B7[7] buffer span12_vert_14 lc_trk_g0_6 +!B14[4],!B15[4],!B15[5],B15[6],B15[7] buffer span12_vert_14 lc_trk_g1_6 +!B6[5],B6[6],B6[7],!B6[8],!B7[8] buffer span12_vert_15 lc_trk_g0_7 +!B14[5],B14[6],B14[7],!B14[8],!B15[8] buffer span12_vert_15 lc_trk_g1_7 +!B0[4],B1[4],!B1[5],B1[6],B1[7] buffer span12_vert_16 lc_trk_g0_0 +!B8[4],B9[4],!B9[5],B9[6],B9[7] buffer span12_vert_16 lc_trk_g1_0 +!B0[5],B0[6],B0[7],!B0[8],B1[8] buffer span12_vert_17 lc_trk_g0_1 +!B8[5],B8[6],B8[7],!B8[8],B9[8] buffer span12_vert_17 lc_trk_g1_1 +!B2[4],B3[4],!B3[5],B3[6],B3[7] buffer span12_vert_18 lc_trk_g0_2 +!B10[4],B11[4],!B11[5],B11[6],B11[7] buffer span12_vert_18 lc_trk_g1_2 +!B2[5],B2[6],B2[7],!B2[8],B3[8] buffer span12_vert_19 lc_trk_g0_3 +!B10[5],B10[6],B10[7],!B10[8],B11[8] buffer span12_vert_19 lc_trk_g1_3 +B2[4],B3[4],B3[5],!B3[6],B3[7] buffer span12_vert_2 lc_trk_g0_2 +B10[4],B11[4],B11[5],!B11[6],B11[7] buffer span12_vert_2 lc_trk_g1_2 +!B4[4],B5[4],!B5[5],B5[6],B5[7] buffer span12_vert_20 lc_trk_g0_4 +!B12[4],B13[4],!B13[5],B13[6],B13[7] buffer span12_vert_20 lc_trk_g1_4 +!B4[5],B4[6],B4[7],!B4[8],B5[8] buffer span12_vert_21 lc_trk_g0_5 +!B12[5],B12[6],B12[7],!B12[8],B13[8] buffer span12_vert_21 lc_trk_g1_5 +!B6[4],B7[4],!B7[5],B7[6],B7[7] buffer span12_vert_22 lc_trk_g0_6 +!B14[4],B15[4],!B15[5],B15[6],B15[7] buffer span12_vert_22 lc_trk_g1_6 +!B6[5],B6[6],B6[7],!B6[8],B7[8] buffer span12_vert_23 lc_trk_g0_7 +!B14[5],B14[6],B14[7],!B14[8],B15[8] buffer span12_vert_23 lc_trk_g1_7 +B2[5],!B2[6],B2[7],B2[8],B3[8] buffer span12_vert_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],B10[8],B11[8] buffer span12_vert_3 lc_trk_g1_3 +B4[4],B5[4],B5[5],!B5[6],B5[7] buffer span12_vert_4 lc_trk_g0_4 +B12[4],B13[4],B13[5],!B13[6],B13[7] buffer span12_vert_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],B4[8],B5[8] buffer span12_vert_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],B12[8],B13[8] buffer span12_vert_5 lc_trk_g1_5 +B6[4],B7[4],B7[5],!B7[6],B7[7] buffer span12_vert_6 lc_trk_g0_6 +B14[4],B15[4],B15[5],!B15[6],B15[7] buffer span12_vert_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],B6[8],B7[8] buffer span12_vert_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],B14[8],B15[8] buffer span12_vert_7 lc_trk_g1_7 +!B0[4],!B1[4],!B1[5],B1[6],B1[7] buffer span12_vert_8 lc_trk_g0_0 +!B8[4],!B9[4],!B9[5],B9[6],B9[7] buffer span12_vert_8 lc_trk_g1_0 +!B0[5],B0[6],B0[7],!B0[8],!B1[8] buffer span12_vert_9 lc_trk_g0_1 +!B8[5],B8[6],B8[7],!B8[8],!B9[8] buffer span12_vert_9 lc_trk_g1_1 +B0[4],!B1[4],!B1[5],B1[6],B1[7] buffer span4_horz_0 lc_trk_g0_0 +B8[4],!B9[4],!B9[5],B9[6],B9[7] buffer span4_horz_0 lc_trk_g1_0 +!B0[5],B0[6],B0[7],B0[8],!B1[8] buffer span4_horz_1 lc_trk_g0_1 +!B8[5],B8[6],B8[7],B8[8],!B9[8] buffer span4_horz_1 lc_trk_g1_1 +B2[4],B3[4],!B3[5],B3[6],B3[7] buffer span4_horz_10 lc_trk_g0_2 +B10[4],B11[4],!B11[5],B11[6],B11[7] buffer span4_horz_10 lc_trk_g1_2 +!B2[5],B2[6],B2[7],B2[8],B3[8] buffer span4_horz_11 lc_trk_g0_3 +!B10[5],B10[6],B10[7],B10[8],B11[8] buffer span4_horz_11 lc_trk_g1_3 +B4[4],B5[4],!B5[5],B5[6],B5[7] buffer span4_horz_12 lc_trk_g0_4 +B12[4],B13[4],!B13[5],B13[6],B13[7] buffer span4_horz_12 lc_trk_g1_4 +!B4[5],B4[6],B4[7],B4[8],B5[8] buffer span4_horz_13 lc_trk_g0_5 +!B12[5],B12[6],B12[7],B12[8],B13[8] buffer span4_horz_13 lc_trk_g1_5 +B6[4],B7[4],!B7[5],B7[6],B7[7] buffer span4_horz_14 lc_trk_g0_6 +B14[4],B15[4],!B15[5],B15[6],B15[7] buffer span4_horz_14 lc_trk_g1_6 +!B6[5],B6[6],B6[7],B6[8],B7[8] buffer span4_horz_15 lc_trk_g0_7 +!B14[5],B14[6],B14[7],B14[8],B15[8] buffer span4_horz_15 lc_trk_g1_7 +!B0[4],!B1[4],B1[5],B1[6],B1[7] buffer span4_horz_16 lc_trk_g0_0 +!B8[4],!B9[4],B9[5],B9[6],B9[7] buffer span4_horz_16 lc_trk_g1_0 +B0[5],B0[6],B0[7],!B0[8],!B1[8] buffer span4_horz_17 lc_trk_g0_1 +B8[5],B8[6],B8[7],!B8[8],!B9[8] buffer span4_horz_17 lc_trk_g1_1 +!B2[4],!B3[4],B3[5],B3[6],B3[7] buffer span4_horz_18 lc_trk_g0_2 +!B10[4],!B11[4],B11[5],B11[6],B11[7] buffer span4_horz_18 lc_trk_g1_2 +B2[5],B2[6],B2[7],!B2[8],!B3[8] buffer span4_horz_19 lc_trk_g0_3 +B10[5],B10[6],B10[7],!B10[8],!B11[8] buffer span4_horz_19 lc_trk_g1_3 +B2[4],!B3[4],!B3[5],B3[6],B3[7] buffer span4_horz_2 lc_trk_g0_2 +B10[4],!B11[4],!B11[5],B11[6],B11[7] buffer span4_horz_2 lc_trk_g1_2 +!B4[4],!B5[4],B5[5],B5[6],B5[7] buffer span4_horz_20 lc_trk_g0_4 +!B12[4],!B13[4],B13[5],B13[6],B13[7] buffer span4_horz_20 lc_trk_g1_4 +B4[5],B4[6],B4[7],!B4[8],!B5[8] buffer span4_horz_21 lc_trk_g0_5 +B12[5],B12[6],B12[7],!B12[8],!B13[8] buffer span4_horz_21 lc_trk_g1_5 +!B6[4],!B7[4],B7[5],B7[6],B7[7] buffer span4_horz_22 lc_trk_g0_6 +!B14[4],!B15[4],B15[5],B15[6],B15[7] buffer span4_horz_22 lc_trk_g1_6 +B6[5],B6[6],B6[7],!B6[8],!B7[8] buffer span4_horz_23 lc_trk_g0_7 +B14[5],B14[6],B14[7],!B14[8],!B15[8] buffer span4_horz_23 lc_trk_g1_7 +!B0[4],B1[4],B1[5],B1[6],B1[7] buffer span4_horz_24 lc_trk_g0_0 +!B8[4],B9[4],B9[5],B9[6],B9[7] buffer span4_horz_24 lc_trk_g1_0 +B0[5],B0[6],B0[7],!B0[8],B1[8] buffer span4_horz_25 lc_trk_g0_1 +B8[5],B8[6],B8[7],!B8[8],B9[8] buffer span4_horz_25 lc_trk_g1_1 +!B2[4],B3[4],B3[5],B3[6],B3[7] buffer span4_horz_26 lc_trk_g0_2 +!B10[4],B11[4],B11[5],B11[6],B11[7] buffer span4_horz_26 lc_trk_g1_2 +B2[5],B2[6],B2[7],!B2[8],B3[8] buffer span4_horz_27 lc_trk_g0_3 +B10[5],B10[6],B10[7],!B10[8],B11[8] buffer span4_horz_27 lc_trk_g1_3 +!B4[4],B5[4],B5[5],B5[6],B5[7] buffer span4_horz_28 lc_trk_g0_4 +!B12[4],B13[4],B13[5],B13[6],B13[7] buffer span4_horz_28 lc_trk_g1_4 +B4[5],B4[6],B4[7],!B4[8],B5[8] buffer span4_horz_29 lc_trk_g0_5 +B12[5],B12[6],B12[7],!B12[8],B13[8] buffer span4_horz_29 lc_trk_g1_5 +!B2[5],B2[6],B2[7],B2[8],!B3[8] buffer span4_horz_3 lc_trk_g0_3 +!B10[5],B10[6],B10[7],B10[8],!B11[8] buffer span4_horz_3 lc_trk_g1_3 +!B6[4],B7[4],B7[5],B7[6],B7[7] buffer span4_horz_30 lc_trk_g0_6 +!B14[4],B15[4],B15[5],B15[6],B15[7] buffer span4_horz_30 lc_trk_g1_6 +B6[5],B6[6],B6[7],!B6[8],B7[8] buffer span4_horz_31 lc_trk_g0_7 +B14[5],B14[6],B14[7],!B14[8],B15[8] buffer span4_horz_31 lc_trk_g1_7 +B0[4],!B1[4],B1[5],B1[6],B1[7] buffer span4_horz_32 lc_trk_g0_0 +B8[4],!B9[4],B9[5],B9[6],B9[7] buffer span4_horz_32 lc_trk_g1_0 +B0[5],B0[6],B0[7],B0[8],!B1[8] buffer span4_horz_33 lc_trk_g0_1 +B8[5],B8[6],B8[7],B8[8],!B9[8] buffer span4_horz_33 lc_trk_g1_1 +B2[4],!B3[4],B3[5],B3[6],B3[7] buffer span4_horz_34 lc_trk_g0_2 +B10[4],!B11[4],B11[5],B11[6],B11[7] buffer span4_horz_34 lc_trk_g1_2 +B2[5],B2[6],B2[7],B2[8],!B3[8] buffer span4_horz_35 lc_trk_g0_3 +B10[5],B10[6],B10[7],B10[8],!B11[8] buffer span4_horz_35 lc_trk_g1_3 +B4[4],!B5[4],B5[5],B5[6],B5[7] buffer span4_horz_36 lc_trk_g0_4 +B12[4],!B13[4],B13[5],B13[6],B13[7] buffer span4_horz_36 lc_trk_g1_4 +B4[5],B4[6],B4[7],B4[8],!B5[8] buffer span4_horz_37 lc_trk_g0_5 +B12[5],B12[6],B12[7],B12[8],!B13[8] buffer span4_horz_37 lc_trk_g1_5 +B6[4],!B7[4],B7[5],B7[6],B7[7] buffer span4_horz_38 lc_trk_g0_6 +B14[4],!B15[4],B15[5],B15[6],B15[7] buffer span4_horz_38 lc_trk_g1_6 +B6[5],B6[6],B6[7],B6[8],!B7[8] buffer span4_horz_39 lc_trk_g0_7 +B14[5],B14[6],B14[7],B14[8],!B15[8] buffer span4_horz_39 lc_trk_g1_7 +B4[4],!B5[4],!B5[5],B5[6],B5[7] buffer span4_horz_4 lc_trk_g0_4 +B12[4],!B13[4],!B13[5],B13[6],B13[7] buffer span4_horz_4 lc_trk_g1_4 +B0[4],B1[4],B1[5],B1[6],B1[7] buffer span4_horz_40 lc_trk_g0_0 +B8[4],B9[4],B9[5],B9[6],B9[7] buffer span4_horz_40 lc_trk_g1_0 +B0[5],B0[6],B0[7],B0[8],B1[8] buffer span4_horz_41 lc_trk_g0_1 +B8[5],B8[6],B8[7],B8[8],B9[8] buffer span4_horz_41 lc_trk_g1_1 +B2[4],B3[4],B3[5],B3[6],B3[7] buffer span4_horz_42 lc_trk_g0_2 +B10[4],B11[4],B11[5],B11[6],B11[7] buffer span4_horz_42 lc_trk_g1_2 +B2[5],B2[6],B2[7],B2[8],B3[8] buffer span4_horz_43 lc_trk_g0_3 +B10[5],B10[6],B10[7],B10[8],B11[8] buffer span4_horz_43 lc_trk_g1_3 +B4[4],B5[4],B5[5],B5[6],B5[7] buffer span4_horz_44 lc_trk_g0_4 +B12[4],B13[4],B13[5],B13[6],B13[7] buffer span4_horz_44 lc_trk_g1_4 +B4[5],B4[6],B4[7],B4[8],B5[8] buffer span4_horz_45 lc_trk_g0_5 +B12[5],B12[6],B12[7],B12[8],B13[8] buffer span4_horz_45 lc_trk_g1_5 +B6[4],B7[4],B7[5],B7[6],B7[7] buffer span4_horz_46 lc_trk_g0_6 +B14[4],B15[4],B15[5],B15[6],B15[7] buffer span4_horz_46 lc_trk_g1_6 +B6[5],B6[6],B6[7],B6[8],B7[8] buffer span4_horz_47 lc_trk_g0_7 +B14[5],B14[6],B14[7],B14[8],B15[8] buffer span4_horz_47 lc_trk_g1_7 +!B4[5],B4[6],B4[7],B4[8],!B5[8] buffer span4_horz_5 lc_trk_g0_5 +!B12[5],B12[6],B12[7],B12[8],!B13[8] buffer span4_horz_5 lc_trk_g1_5 +B6[4],!B7[4],!B7[5],B7[6],B7[7] buffer span4_horz_6 lc_trk_g0_6 +B14[4],!B15[4],!B15[5],B15[6],B15[7] buffer span4_horz_6 lc_trk_g1_6 +!B6[5],B6[6],B6[7],B6[8],!B7[8] buffer span4_horz_7 lc_trk_g0_7 +!B14[5],B14[6],B14[7],B14[8],!B15[8] buffer span4_horz_7 lc_trk_g1_7 +B0[4],B1[4],!B1[5],B1[6],B1[7] buffer span4_horz_8 lc_trk_g0_0 +B8[4],B9[4],!B9[5],B9[6],B9[7] buffer span4_horz_8 lc_trk_g1_0 +!B0[5],B0[6],B0[7],B0[8],B1[8] buffer span4_horz_9 lc_trk_g0_1 +!B8[5],B8[6],B8[7],B8[8],B9[8] buffer span4_horz_9 lc_trk_g1_1 +!B0[4],B1[4],B1[5],!B1[6],B1[7] buffer span4_horz_r_0 lc_trk_g0_0 +!B8[4],B9[4],B9[5],!B9[6],B9[7] buffer span4_horz_r_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],!B0[8],B1[8] buffer span4_horz_r_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],!B8[8],B9[8] buffer span4_horz_r_1 lc_trk_g1_1 +B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer span4_horz_r_10 lc_trk_g0_2 +B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer span4_horz_r_10 lc_trk_g1_2 +B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer span4_horz_r_11 lc_trk_g0_3 +B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer span4_horz_r_11 lc_trk_g1_3 +B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer span4_horz_r_12 lc_trk_g0_4 +B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer span4_horz_r_12 lc_trk_g1_4 +B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer span4_horz_r_13 lc_trk_g0_5 +B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer span4_horz_r_13 lc_trk_g1_5 +B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer span4_horz_r_14 lc_trk_g0_6 +B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer span4_horz_r_14 lc_trk_g1_6 +B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer span4_horz_r_15 lc_trk_g0_7 +B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer span4_horz_r_15 lc_trk_g1_7 +!B2[4],B3[4],B3[5],!B3[6],B3[7] buffer span4_horz_r_2 lc_trk_g0_2 +!B10[4],B11[4],B11[5],!B11[6],B11[7] buffer span4_horz_r_2 lc_trk_g1_2 +B2[5],!B2[6],B2[7],!B2[8],B3[8] buffer span4_horz_r_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],!B10[8],B11[8] buffer span4_horz_r_3 lc_trk_g1_3 +!B4[4],B5[4],B5[5],!B5[6],B5[7] buffer span4_horz_r_4 lc_trk_g0_4 +!B12[4],B13[4],B13[5],!B13[6],B13[7] buffer span4_horz_r_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],!B4[8],B5[8] buffer span4_horz_r_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],!B12[8],B13[8] buffer span4_horz_r_5 lc_trk_g1_5 +!B6[4],B7[4],B7[5],!B7[6],B7[7] buffer span4_horz_r_6 lc_trk_g0_6 +!B14[4],B15[4],B15[5],!B15[6],B15[7] buffer span4_horz_r_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],!B6[8],B7[8] buffer span4_horz_r_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],!B14[8],B15[8] buffer span4_horz_r_7 lc_trk_g1_7 +B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer span4_horz_r_8 lc_trk_g0_0 +B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer span4_horz_r_8 lc_trk_g1_0 +B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer span4_horz_r_9 lc_trk_g0_1 +B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer span4_horz_r_9 lc_trk_g1_1 +B0[4],!B1[4],!B1[5],B1[6],B1[7] buffer span4_vert_0 lc_trk_g0_0 +B8[4],!B9[4],!B9[5],B9[6],B9[7] buffer span4_vert_0 lc_trk_g1_0 +!B0[5],B0[6],B0[7],B0[8],!B1[8] buffer span4_vert_1 lc_trk_g0_1 +!B8[5],B8[6],B8[7],B8[8],!B9[8] buffer span4_vert_1 lc_trk_g1_1 +B2[4],B3[4],!B3[5],B3[6],B3[7] buffer span4_vert_10 lc_trk_g0_2 +B10[4],B11[4],!B11[5],B11[6],B11[7] buffer span4_vert_10 lc_trk_g1_2 +!B2[5],B2[6],B2[7],B2[8],B3[8] buffer span4_vert_11 lc_trk_g0_3 +!B10[5],B10[6],B10[7],B10[8],B11[8] buffer span4_vert_11 lc_trk_g1_3 +B4[4],B5[4],!B5[5],B5[6],B5[7] buffer span4_vert_12 lc_trk_g0_4 +B12[4],B13[4],!B13[5],B13[6],B13[7] buffer span4_vert_12 lc_trk_g1_4 +!B4[5],B4[6],B4[7],B4[8],B5[8] buffer span4_vert_13 lc_trk_g0_5 +!B12[5],B12[6],B12[7],B12[8],B13[8] buffer span4_vert_13 lc_trk_g1_5 +B6[4],B7[4],!B7[5],B7[6],B7[7] buffer span4_vert_14 lc_trk_g0_6 +B14[4],B15[4],!B15[5],B15[6],B15[7] buffer span4_vert_14 lc_trk_g1_6 +!B6[5],B6[6],B6[7],B6[8],B7[8] buffer span4_vert_15 lc_trk_g0_7 +!B14[5],B14[6],B14[7],B14[8],B15[8] buffer span4_vert_15 lc_trk_g1_7 +!B0[4],!B1[4],B1[5],B1[6],B1[7] buffer span4_vert_16 lc_trk_g0_0 +!B8[4],!B9[4],B9[5],B9[6],B9[7] buffer span4_vert_16 lc_trk_g1_0 +B0[5],B0[6],B0[7],!B0[8],!B1[8] buffer span4_vert_17 lc_trk_g0_1 +B8[5],B8[6],B8[7],!B8[8],!B9[8] buffer span4_vert_17 lc_trk_g1_1 +!B2[4],!B3[4],B3[5],B3[6],B3[7] buffer span4_vert_18 lc_trk_g0_2 +!B10[4],!B11[4],B11[5],B11[6],B11[7] buffer span4_vert_18 lc_trk_g1_2 +B2[5],B2[6],B2[7],!B2[8],!B3[8] buffer span4_vert_19 lc_trk_g0_3 +B10[5],B10[6],B10[7],!B10[8],!B11[8] buffer span4_vert_19 lc_trk_g1_3 +B2[4],!B3[4],!B3[5],B3[6],B3[7] buffer span4_vert_2 lc_trk_g0_2 +B10[4],!B11[4],!B11[5],B11[6],B11[7] buffer span4_vert_2 lc_trk_g1_2 +!B4[4],!B5[4],B5[5],B5[6],B5[7] buffer span4_vert_20 lc_trk_g0_4 +!B12[4],!B13[4],B13[5],B13[6],B13[7] buffer span4_vert_20 lc_trk_g1_4 +B4[5],B4[6],B4[7],!B4[8],!B5[8] buffer span4_vert_21 lc_trk_g0_5 +B12[5],B12[6],B12[7],!B12[8],!B13[8] buffer span4_vert_21 lc_trk_g1_5 +!B6[4],!B7[4],B7[5],B7[6],B7[7] buffer span4_vert_22 lc_trk_g0_6 +!B14[4],!B15[4],B15[5],B15[6],B15[7] buffer span4_vert_22 lc_trk_g1_6 +B6[5],B6[6],B6[7],!B6[8],!B7[8] buffer span4_vert_23 lc_trk_g0_7 +B14[5],B14[6],B14[7],!B14[8],!B15[8] buffer span4_vert_23 lc_trk_g1_7 +!B0[4],B1[4],B1[5],B1[6],B1[7] buffer span4_vert_24 lc_trk_g0_0 +!B8[4],B9[4],B9[5],B9[6],B9[7] buffer span4_vert_24 lc_trk_g1_0 +B0[5],B0[6],B0[7],!B0[8],B1[8] buffer span4_vert_25 lc_trk_g0_1 +B8[5],B8[6],B8[7],!B8[8],B9[8] buffer span4_vert_25 lc_trk_g1_1 +!B2[4],B3[4],B3[5],B3[6],B3[7] buffer span4_vert_26 lc_trk_g0_2 +!B10[4],B11[4],B11[5],B11[6],B11[7] buffer span4_vert_26 lc_trk_g1_2 +B2[5],B2[6],B2[7],!B2[8],B3[8] buffer span4_vert_27 lc_trk_g0_3 +B10[5],B10[6],B10[7],!B10[8],B11[8] buffer span4_vert_27 lc_trk_g1_3 +!B4[4],B5[4],B5[5],B5[6],B5[7] buffer span4_vert_28 lc_trk_g0_4 +!B12[4],B13[4],B13[5],B13[6],B13[7] buffer span4_vert_28 lc_trk_g1_4 +B4[5],B4[6],B4[7],!B4[8],B5[8] buffer span4_vert_29 lc_trk_g0_5 +B12[5],B12[6],B12[7],!B12[8],B13[8] buffer span4_vert_29 lc_trk_g1_5 +!B2[5],B2[6],B2[7],B2[8],!B3[8] buffer span4_vert_3 lc_trk_g0_3 +!B10[5],B10[6],B10[7],B10[8],!B11[8] buffer span4_vert_3 lc_trk_g1_3 +!B6[4],B7[4],B7[5],B7[6],B7[7] buffer span4_vert_30 lc_trk_g0_6 +!B14[4],B15[4],B15[5],B15[6],B15[7] buffer span4_vert_30 lc_trk_g1_6 +B6[5],B6[6],B6[7],!B6[8],B7[8] buffer span4_vert_31 lc_trk_g0_7 +B14[5],B14[6],B14[7],!B14[8],B15[8] buffer span4_vert_31 lc_trk_g1_7 +B0[4],!B1[4],B1[5],B1[6],B1[7] buffer span4_vert_32 lc_trk_g0_0 +B8[4],!B9[4],B9[5],B9[6],B9[7] buffer span4_vert_32 lc_trk_g1_0 +B0[5],B0[6],B0[7],B0[8],!B1[8] buffer span4_vert_33 lc_trk_g0_1 +B8[5],B8[6],B8[7],B8[8],!B9[8] buffer span4_vert_33 lc_trk_g1_1 +B2[4],!B3[4],B3[5],B3[6],B3[7] buffer span4_vert_34 lc_trk_g0_2 +B10[4],!B11[4],B11[5],B11[6],B11[7] buffer span4_vert_34 lc_trk_g1_2 +B2[5],B2[6],B2[7],B2[8],!B3[8] buffer span4_vert_35 lc_trk_g0_3 +B10[5],B10[6],B10[7],B10[8],!B11[8] buffer span4_vert_35 lc_trk_g1_3 +B4[4],!B5[4],B5[5],B5[6],B5[7] buffer span4_vert_36 lc_trk_g0_4 +B12[4],!B13[4],B13[5],B13[6],B13[7] buffer span4_vert_36 lc_trk_g1_4 +B4[5],B4[6],B4[7],B4[8],!B5[8] buffer span4_vert_37 lc_trk_g0_5 +B12[5],B12[6],B12[7],B12[8],!B13[8] buffer span4_vert_37 lc_trk_g1_5 +B6[4],!B7[4],B7[5],B7[6],B7[7] buffer span4_vert_38 lc_trk_g0_6 +B14[4],!B15[4],B15[5],B15[6],B15[7] buffer span4_vert_38 lc_trk_g1_6 +B6[5],B6[6],B6[7],B6[8],!B7[8] buffer span4_vert_39 lc_trk_g0_7 +B14[5],B14[6],B14[7],B14[8],!B15[8] buffer span4_vert_39 lc_trk_g1_7 +B4[4],!B5[4],!B5[5],B5[6],B5[7] buffer span4_vert_4 lc_trk_g0_4 +B12[4],!B13[4],!B13[5],B13[6],B13[7] buffer span4_vert_4 lc_trk_g1_4 +B0[4],B1[4],B1[5],B1[6],B1[7] buffer span4_vert_40 lc_trk_g0_0 +B8[4],B9[4],B9[5],B9[6],B9[7] buffer span4_vert_40 lc_trk_g1_0 +B0[5],B0[6],B0[7],B0[8],B1[8] buffer span4_vert_41 lc_trk_g0_1 +B8[5],B8[6],B8[7],B8[8],B9[8] buffer span4_vert_41 lc_trk_g1_1 +B2[4],B3[4],B3[5],B3[6],B3[7] buffer span4_vert_42 lc_trk_g0_2 +B10[4],B11[4],B11[5],B11[6],B11[7] buffer span4_vert_42 lc_trk_g1_2 +B2[5],B2[6],B2[7],B2[8],B3[8] buffer span4_vert_43 lc_trk_g0_3 +B10[5],B10[6],B10[7],B10[8],B11[8] buffer span4_vert_43 lc_trk_g1_3 +B4[4],B5[4],B5[5],B5[6],B5[7] buffer span4_vert_44 lc_trk_g0_4 +B12[4],B13[4],B13[5],B13[6],B13[7] buffer span4_vert_44 lc_trk_g1_4 +B4[5],B4[6],B4[7],B4[8],B5[8] buffer span4_vert_45 lc_trk_g0_5 +B12[5],B12[6],B12[7],B12[8],B13[8] buffer span4_vert_45 lc_trk_g1_5 +B6[4],B7[4],B7[5],B7[6],B7[7] buffer span4_vert_46 lc_trk_g0_6 +B14[4],B15[4],B15[5],B15[6],B15[7] buffer span4_vert_46 lc_trk_g1_6 +B6[5],B6[6],B6[7],B6[8],B7[8] buffer span4_vert_47 lc_trk_g0_7 +B14[5],B14[6],B14[7],B14[8],B15[8] buffer span4_vert_47 lc_trk_g1_7 +!B4[5],B4[6],B4[7],B4[8],!B5[8] buffer span4_vert_5 lc_trk_g0_5 +!B12[5],B12[6],B12[7],B12[8],!B13[8] buffer span4_vert_5 lc_trk_g1_5 +B6[4],!B7[4],!B7[5],B7[6],B7[7] buffer span4_vert_6 lc_trk_g0_6 +B14[4],!B15[4],!B15[5],B15[6],B15[7] buffer span4_vert_6 lc_trk_g1_6 +!B6[5],B6[6],B6[7],B6[8],!B7[8] buffer span4_vert_7 lc_trk_g0_7 +!B14[5],B14[6],B14[7],B14[8],!B15[8] buffer span4_vert_7 lc_trk_g1_7 +B0[4],B1[4],!B1[5],B1[6],B1[7] buffer span4_vert_8 lc_trk_g0_0 +B8[4],B9[4],!B9[5],B9[6],B9[7] buffer span4_vert_8 lc_trk_g1_0 +!B0[5],B0[6],B0[7],B0[8],B1[8] buffer span4_vert_9 lc_trk_g0_1 +!B8[5],B8[6],B8[7],B8[8],B9[8] buffer span4_vert_9 lc_trk_g1_1 +!B0[4],B1[4],B1[5],!B1[6],B1[7] buffer span4_vert_b_0 lc_trk_g0_0 +!B8[4],B9[4],B9[5],!B9[6],B9[7] buffer span4_vert_b_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],!B0[8],B1[8] buffer span4_vert_b_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],!B8[8],B9[8] buffer span4_vert_b_1 lc_trk_g1_1 +B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer span4_vert_b_10 lc_trk_g0_2 +B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer span4_vert_b_10 lc_trk_g1_2 +B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer span4_vert_b_11 lc_trk_g0_3 +B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer span4_vert_b_11 lc_trk_g1_3 +B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer span4_vert_b_12 lc_trk_g0_4 +B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer span4_vert_b_12 lc_trk_g1_4 +B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer span4_vert_b_13 lc_trk_g0_5 +B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer span4_vert_b_13 lc_trk_g1_5 +B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer span4_vert_b_14 lc_trk_g0_6 +B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer span4_vert_b_14 lc_trk_g1_6 +B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer span4_vert_b_15 lc_trk_g0_7 +B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer span4_vert_b_15 lc_trk_g1_7 +!B2[4],B3[4],B3[5],!B3[6],B3[7] buffer span4_vert_b_2 lc_trk_g0_2 +!B10[4],B11[4],B11[5],!B11[6],B11[7] buffer span4_vert_b_2 lc_trk_g1_2 +B2[5],!B2[6],B2[7],!B2[8],B3[8] buffer span4_vert_b_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],!B10[8],B11[8] buffer span4_vert_b_3 lc_trk_g1_3 +!B4[4],B5[4],B5[5],!B5[6],B5[7] buffer span4_vert_b_4 lc_trk_g0_4 +!B12[4],B13[4],B13[5],!B13[6],B13[7] buffer span4_vert_b_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],!B4[8],B5[8] buffer span4_vert_b_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],!B12[8],B13[8] buffer span4_vert_b_5 lc_trk_g1_5 +!B6[4],B7[4],B7[5],!B7[6],B7[7] buffer span4_vert_b_6 lc_trk_g0_6 +!B14[4],B15[4],B15[5],!B15[6],B15[7] buffer span4_vert_b_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],!B6[8],B7[8] buffer span4_vert_b_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],!B14[8],B15[8] buffer span4_vert_b_7 lc_trk_g1_7 +B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer span4_vert_b_8 lc_trk_g0_0 +B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer span4_vert_b_8 lc_trk_g1_0 +B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer span4_vert_b_9 lc_trk_g0_1 +B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer span4_vert_b_9 lc_trk_g1_1 +B1[17] buffer wire_io_cluster/io_0/D_IN_0 span12_horz_0 +B5[17] buffer wire_io_cluster/io_0/D_IN_0 span12_horz_16 +B2[17] buffer wire_io_cluster/io_0/D_IN_0 span12_horz_8 +B1[17] buffer wire_io_cluster/io_0/D_IN_0 span12_vert_0 +B5[17] buffer wire_io_cluster/io_0/D_IN_0 span12_vert_16 +B2[17] buffer wire_io_cluster/io_0/D_IN_0 span12_vert_8 +B1[0] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_0 +B0[0] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_16 +B0[1] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_24 +B1[2] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_32 +B3[0] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_40 +B1[1] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_8 +B3[1] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_r_0 +B3[2] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_r_12 +B2[0] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_r_4 +B2[1] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_r_8 +B1[0] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_0 +B0[0] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_16 +B0[1] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_24 +B1[2] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_32 +B3[0] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_40 +B1[1] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_8 +B3[1] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_b_0 +B3[2] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_b_12 +B2[0] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_b_4 +B2[1] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_b_8 +B7[17] buffer wire_io_cluster/io_0/D_IN_1 span12_horz_10 +B6[16] buffer wire_io_cluster/io_0/D_IN_1 span12_horz_18 +B7[16] buffer wire_io_cluster/io_0/D_IN_1 span12_horz_2 +B7[17] buffer wire_io_cluster/io_0/D_IN_1 span12_vert_10 +B6[16] buffer wire_io_cluster/io_0/D_IN_1 span12_vert_18 +B7[16] buffer wire_io_cluster/io_0/D_IN_1 span12_vert_2 +B5[1] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_10 +B4[0] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_18 +B5[0] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_2 +B4[1] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_26 +B5[2] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_34 +B7[0] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_42 +B7[1] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_1 +B7[2] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_13 +B6[0] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_5 +B6[1] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_9 +B4[0] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_18 +B5[0] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_2 +B4[1] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_26 +B5[2] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_34 +B7[0] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_42 +B7[1] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_b_1 +B7[2] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_b_13 +B6[0] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_b_5 +B6[1] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_b_9 +B9[17] buffer wire_io_cluster/io_1/D_IN_0 span12_horz_12 +B8[16] buffer wire_io_cluster/io_1/D_IN_0 span12_horz_20 +B9[16] buffer wire_io_cluster/io_1/D_IN_0 span12_horz_4 +B9[17] buffer wire_io_cluster/io_1/D_IN_0 span12_vert_12 +B8[16] buffer wire_io_cluster/io_1/D_IN_0 span12_vert_20 +B9[16] buffer wire_io_cluster/io_1/D_IN_0 span12_vert_4 +B9[1] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_12 +B8[0] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_20 +B8[1] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_28 +B9[2] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_36 +B9[0] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_4 +B11[0] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_44 +B10[1] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_r_10 +B11[2] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_r_14 +B11[1] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_r_2 +B10[0] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_r_6 +B9[1] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_12 +B8[0] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_20 +B8[1] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_28 +B9[2] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_36 +B9[0] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_4 +B11[0] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_44 +B10[1] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_b_10 +B11[2] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_b_14 +B11[1] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_b_2 +B10[0] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_b_6 +B12[17] buffer wire_io_cluster/io_1/D_IN_1 span12_horz_14 +B15[17] buffer wire_io_cluster/io_1/D_IN_1 span12_horz_22 +B11[17] buffer wire_io_cluster/io_1/D_IN_1 span12_horz_6 +B12[17] buffer wire_io_cluster/io_1/D_IN_1 span12_vert_14 +B15[17] buffer wire_io_cluster/io_1/D_IN_1 span12_vert_22 +B11[17] buffer wire_io_cluster/io_1/D_IN_1 span12_vert_6 +B13[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_14 +B12[0] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_22 +B12[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_30 +B13[2] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_38 +B13[0] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_6 +B14[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_r_11 +B15[2] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_r_15 +B15[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_r_3 +B14[0] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_r_7 +B13[1] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_14 +B12[0] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_22 +B12[1] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_30 +B13[2] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_38 +B15[0] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_46 +B13[0] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_6 +B14[1] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_b_11 +B15[2] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_b_15 +B15[1] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_b_3 +B14[0] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_b_7 +B1[11],B1[12] routing span4_horz_1 span4_horz_25 +B1[13],B1[14] routing span4_horz_1 span4_vert_b_0 +B0[11],B0[12] routing span4_horz_1 span4_vert_t_12 +B7[11],B7[12] routing span4_horz_13 span4_horz_37 +B7[13],B7[14] routing span4_horz_13 span4_vert_b_2 +B6[11],B6[12] routing span4_horz_13 span4_vert_t_14 +B13[11],B13[12] routing span4_horz_19 span4_horz_43 +B13[13],B13[14] routing span4_horz_19 span4_vert_b_3 +B12[11],B12[12] routing span4_horz_19 span4_vert_t_15 +B0[13],!B0[14] routing span4_horz_25 span4_horz_1 +B1[13],!B1[14] routing span4_horz_25 span4_vert_b_0 +!B0[11],B0[12] routing span4_horz_25 span4_vert_t_12 +B2[13],!B2[14] routing span4_horz_31 span4_horz_7 +B3[13],!B3[14] routing span4_horz_31 span4_vert_b_1 +!B2[11],B2[12] routing span4_horz_31 span4_vert_t_13 +B6[13],!B6[14] routing span4_horz_37 span4_horz_13 +B7[13],!B7[14] routing span4_horz_37 span4_vert_b_2 +!B6[11],B6[12] routing span4_horz_37 span4_vert_t_14 +B12[13],!B12[14] routing span4_horz_43 span4_horz_19 +B13[13],!B13[14] routing span4_horz_43 span4_vert_b_3 +!B12[11],B12[12] routing span4_horz_43 span4_vert_t_15 +B3[11],B3[12] routing span4_horz_7 span4_horz_31 +B3[13],B3[14] routing span4_horz_7 span4_vert_b_1 +B2[11],B2[12] routing span4_horz_7 span4_vert_t_13 +!B1[13],B1[14] routing span4_horz_l_12 span4_horz_r_0 +!B0[13],B0[14] routing span4_horz_l_12 span4_vert_1 +B1[11],!B1[12] routing span4_horz_l_12 span4_vert_25 +!B3[13],B3[14] routing span4_horz_l_13 span4_horz_r_1 +B3[11],!B3[12] routing span4_horz_l_13 span4_vert_31 +!B2[13],B2[14] routing span4_horz_l_13 span4_vert_7 +!B7[13],B7[14] routing span4_horz_l_14 span4_horz_r_2 +!B6[13],B6[14] routing span4_horz_l_14 span4_vert_13 +B7[11],!B7[12] routing span4_horz_l_14 span4_vert_37 +!B13[13],B13[14] routing span4_horz_l_15 span4_horz_r_3 +!B12[13],B12[14] routing span4_horz_l_15 span4_vert_19 +B13[11],!B13[12] routing span4_horz_l_15 span4_vert_43 +B0[11],!B0[12] routing span4_horz_r_0 span4_horz_l_12 +B0[13],B0[14] routing span4_horz_r_0 span4_vert_1 +!B1[11],B1[12] routing span4_horz_r_0 span4_vert_25 +B2[11],!B2[12] routing span4_horz_r_1 span4_horz_l_13 +!B3[11],B3[12] routing span4_horz_r_1 span4_vert_31 +B2[13],B2[14] routing span4_horz_r_1 span4_vert_7 +B6[11],!B6[12] routing span4_horz_r_2 span4_horz_l_14 +B6[13],B6[14] routing span4_horz_r_2 span4_vert_13 +!B7[11],B7[12] routing span4_horz_r_2 span4_vert_37 +B12[11],!B12[12] routing span4_horz_r_3 span4_horz_l_15 +B12[13],B12[14] routing span4_horz_r_3 span4_vert_19 +!B13[11],B13[12] routing span4_horz_r_3 span4_vert_43 +B0[11],B0[12] routing span4_vert_1 span4_horz_l_12 +B1[13],B1[14] routing span4_vert_1 span4_horz_r_0 +B1[11],B1[12] routing span4_vert_1 span4_vert_25 +B6[11],B6[12] routing span4_vert_13 span4_horz_l_14 +B7[13],B7[14] routing span4_vert_13 span4_horz_r_2 +B7[11],B7[12] routing span4_vert_13 span4_vert_37 +B12[11],B12[12] routing span4_vert_19 span4_horz_l_15 +B13[13],B13[14] routing span4_vert_19 span4_horz_r_3 +B13[11],B13[12] routing span4_vert_19 span4_vert_43 +!B0[11],B0[12] routing span4_vert_25 span4_horz_l_12 +B1[13],!B1[14] routing span4_vert_25 span4_horz_r_0 +B0[13],!B0[14] routing span4_vert_25 span4_vert_1 +!B2[11],B2[12] routing span4_vert_31 span4_horz_l_13 +B3[13],!B3[14] routing span4_vert_31 span4_horz_r_1 +B2[13],!B2[14] routing span4_vert_31 span4_vert_7 +!B6[11],B6[12] routing span4_vert_37 span4_horz_l_14 +B7[13],!B7[14] routing span4_vert_37 span4_horz_r_2 +B6[13],!B6[14] routing span4_vert_37 span4_vert_13 +!B12[11],B12[12] routing span4_vert_43 span4_horz_l_15 +B13[13],!B13[14] routing span4_vert_43 span4_horz_r_3 +B12[13],!B12[14] routing span4_vert_43 span4_vert_19 +B2[11],B2[12] routing span4_vert_7 span4_horz_l_13 +B3[13],B3[14] routing span4_vert_7 span4_horz_r_1 +B3[11],B3[12] routing span4_vert_7 span4_vert_31 +B0[13],B0[14] routing span4_vert_b_0 span4_horz_1 +!B1[11],B1[12] routing span4_vert_b_0 span4_horz_25 +B0[11],!B0[12] routing span4_vert_b_0 span4_vert_t_12 +!B3[11],B3[12] routing span4_vert_b_1 span4_horz_31 +B2[13],B2[14] routing span4_vert_b_1 span4_horz_7 +B2[11],!B2[12] routing span4_vert_b_1 span4_vert_t_13 +B6[13],B6[14] routing span4_vert_b_2 span4_horz_13 +!B7[11],B7[12] routing span4_vert_b_2 span4_horz_37 +B6[11],!B6[12] routing span4_vert_b_2 span4_vert_t_14 +B12[13],B12[14] routing span4_vert_b_3 span4_horz_19 +!B13[11],B13[12] routing span4_vert_b_3 span4_horz_43 +B12[11],!B12[12] routing span4_vert_b_3 span4_vert_t_15 +!B0[13],B0[14] routing span4_vert_t_12 span4_horz_1 +B1[11],!B1[12] routing span4_vert_t_12 span4_horz_25 +!B1[13],B1[14] routing span4_vert_t_12 span4_vert_b_0 +B3[11],!B3[12] routing span4_vert_t_13 span4_horz_31 +!B2[13],B2[14] routing span4_vert_t_13 span4_horz_7 +!B3[13],B3[14] routing span4_vert_t_13 span4_vert_b_1 +!B6[13],B6[14] routing span4_vert_t_14 span4_horz_13 +B7[11],!B7[12] routing span4_vert_t_14 span4_horz_37 +!B7[13],B7[14] routing span4_vert_t_14 span4_vert_b_2 +!B12[13],B12[14] routing span4_vert_t_15 span4_horz_19 +B13[11],!B13[12] routing span4_vert_t_15 span4_horz_43 +!B13[13],B13[14] routing span4_vert_t_15 span4_vert_b_3 +""" +database_logic_txt = """ +B0[1] ColBufCtrl LH_colbuf_cntl_0 B0[1] +B9[7] ColBufCtrl LH_colbuf_cntl_0 B9[7] +B1[2] ColBufCtrl LH_colbuf_cntl_1 B1[2] +B8[7] ColBufCtrl LH_colbuf_cntl_1 B8[7] +B11[7] ColBufCtrl LH_colbuf_cntl_2 B11[7] +B5[2] ColBufCtrl LH_colbuf_cntl_2 B5[2] +B10[7] ColBufCtrl LH_colbuf_cntl_3 B10[7] +B7[2] ColBufCtrl LH_colbuf_cntl_3 B7[2] +B13[7] ColBufCtrl LH_colbuf_cntl_4 B13[7] +B9[2] ColBufCtrl LH_colbuf_cntl_4 B9[2] +B11[2] ColBufCtrl LH_colbuf_cntl_5 B11[2] +B12[7] ColBufCtrl LH_colbuf_cntl_5 B12[7] +B13[2] ColBufCtrl LH_colbuf_cntl_6 B13[2] +B15[7] ColBufCtrl LH_colbuf_cntl_6 B15[7] +B14[7] ColBufCtrl LH_colbuf_cntl_7 B14[7] +B15[2] ColBufCtrl LH_colbuf_cntl_7 B15[2] +B0[36],B0[37],B0[38],B0[39],B0[40],B0[41],B0[42],B0[43],B0[44],B0[45],B1[36],B1[37],B1[38],B1[39],B1[40],B1[41],B1[42],B1[43],B1[44],B1[45] LC_0 +B2[36],B2[37],B2[38],B2[39],B2[40],B2[41],B2[42],B2[43],B2[44],B2[45],B3[36],B3[37],B3[38],B3[39],B3[40],B3[41],B3[42],B3[43],B3[44],B3[45] LC_1 +B4[36],B4[37],B4[38],B4[39],B4[40],B4[41],B4[42],B4[43],B4[44],B4[45],B5[36],B5[37],B5[38],B5[39],B5[40],B5[41],B5[42],B5[43],B5[44],B5[45] LC_2 +B6[36],B6[37],B6[38],B6[39],B6[40],B6[41],B6[42],B6[43],B6[44],B6[45],B7[36],B7[37],B7[38],B7[39],B7[40],B7[41],B7[42],B7[43],B7[44],B7[45] LC_3 +B8[36],B8[37],B8[38],B8[39],B8[40],B8[41],B8[42],B8[43],B8[44],B8[45],B9[36],B9[37],B9[38],B9[39],B9[40],B9[41],B9[42],B9[43],B9[44],B9[45] LC_4 +B10[36],B10[37],B10[38],B10[39],B10[40],B10[41],B10[42],B10[43],B10[44],B10[45],B11[36],B11[37],B11[38],B11[39],B11[40],B11[41],B11[42],B11[43],B11[44],B11[45] LC_5 +B12[36],B12[37],B12[38],B12[39],B12[40],B12[41],B12[42],B12[43],B12[44],B12[45],B13[36],B13[37],B13[38],B13[39],B13[40],B13[41],B13[42],B13[43],B13[44],B13[45] LC_6 +B14[36],B14[37],B14[38],B14[39],B14[40],B14[41],B14[42],B14[43],B14[44],B14[45],B15[36],B15[37],B15[38],B15[39],B15[40],B15[41],B15[42],B15[43],B15[44],B15[45] LC_7 +B0[0] NegClk +B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 +B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 +!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 +!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 +B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 +B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 +!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 +!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 +B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 +B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 +B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 +B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 +!B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer bot_op_0 lc_trk_g0_0 +!B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer bot_op_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer bot_op_1 lc_trk_g1_1 +!B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer bot_op_2 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer bot_op_2 lc_trk_g1_2 +!B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer bot_op_3 lc_trk_g0_3 +!B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer bot_op_3 lc_trk_g1_3 +!B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer bot_op_4 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer bot_op_4 lc_trk_g1_4 +B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer bot_op_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer bot_op_5 lc_trk_g1_5 +!B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer bot_op_6 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer bot_op_6 lc_trk_g1_6 +!B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer bot_op_7 lc_trk_g0_7 +!B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer bot_op_7 lc_trk_g1_7 +!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 +!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 +!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 +!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 +!B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0 +!B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1 +!B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 +!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_logic_cluster/lc_7/clk +!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_logic_cluster/lc_7/s_r +!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 +!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 +!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 +!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 +!B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_logic_cluster/lc_7/cen +!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_logic_cluster/lc_7/clk +B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 +B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 +B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 +B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 +B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_logic_cluster/lc_7/clk +!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_logic_cluster/lc_7/s_r +B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 +B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 +B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 +B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 +!B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_logic_cluster/lc_7/cen +B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_logic_cluster/lc_7/clk +!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 +!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 +!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 +!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 +!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_logic_cluster/lc_7/clk +B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_logic_cluster/lc_7/s_r +!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 +!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 +!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 +B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_logic_cluster/lc_7/cen +!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_logic_cluster/lc_7/clk +B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 +B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 +B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 +B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 +B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_logic_cluster/lc_7/clk +B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_logic_cluster/lc_7/s_r +B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 +B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 +B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 +B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 +B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_logic_cluster/lc_7/cen +B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_logic_cluster/lc_7/clk +!B0[35],B1[32],!B1[33],!B1[34],!B1[35] buffer lc_trk_g0_0 input_2_0 +!B4[35],B5[32],!B5[33],!B5[34],!B5[35] buffer lc_trk_g0_0 input_2_2 +!B8[35],B9[32],!B9[33],!B9[34],!B9[35] buffer lc_trk_g0_0 input_2_4 +!B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input_2_6 +!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 wire_logic_cluster/lc_0/in_0 +!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_logic_cluster/lc_1/in_1 +!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 wire_logic_cluster/lc_2/in_0 +!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_logic_cluster/lc_3/in_1 +!B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 wire_logic_cluster/lc_4/in_0 +!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_logic_cluster/lc_5/in_1 +!B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 wire_logic_cluster/lc_6/in_0 +!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_logic_cluster/lc_7/clk +!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_logic_cluster/lc_7/in_1 +!B2[35],B3[32],!B3[33],!B3[34],!B3[35] buffer lc_trk_g0_1 input_2_1 +!B6[35],B7[32],!B7[33],!B7[34],!B7[35] buffer lc_trk_g0_1 input_2_3 +!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input_2_5 +!B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input_2_7 +!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_logic_cluster/lc_0/in_1 +!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 wire_logic_cluster/lc_1/in_0 +!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_logic_cluster/lc_2/in_1 +!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 wire_logic_cluster/lc_3/in_0 +!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_logic_cluster/lc_4/in_1 +!B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 wire_logic_cluster/lc_5/in_0 +!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_logic_cluster/lc_6/in_1 +!B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 wire_logic_cluster/lc_7/in_0 +!B0[35],B1[32],!B1[33],!B1[34],B1[35] buffer lc_trk_g0_2 input_2_0 +!B4[35],B5[32],!B5[33],!B5[34],B5[35] buffer lc_trk_g0_2 input_2_2 +!B8[35],B9[32],!B9[33],!B9[34],B9[35] buffer lc_trk_g0_2 input_2_4 +!B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input_2_6 +!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 wire_logic_cluster/lc_0/in_0 +!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_logic_cluster/lc_1/in_1 +!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_logic_cluster/lc_1/in_3 +!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 wire_logic_cluster/lc_2/in_0 +!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_logic_cluster/lc_3/in_1 +!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_logic_cluster/lc_3/in_3 +!B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 wire_logic_cluster/lc_4/in_0 +!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_logic_cluster/lc_5/in_1 +!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_logic_cluster/lc_5/in_3 +!B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 wire_logic_cluster/lc_6/in_0 +!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_logic_cluster/lc_7/cen +!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_logic_cluster/lc_7/in_1 +!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_logic_cluster/lc_7/in_3 +!B2[35],B3[32],!B3[33],!B3[34],B3[35] buffer lc_trk_g0_3 input_2_1 +!B6[35],B7[32],!B7[33],!B7[34],B7[35] buffer lc_trk_g0_3 input_2_3 +!B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input_2_5 +!B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input_2_7 +!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_logic_cluster/lc_0/in_1 +!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_logic_cluster/lc_0/in_3 +!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 wire_logic_cluster/lc_1/in_0 +!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_logic_cluster/lc_2/in_1 +!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_logic_cluster/lc_2/in_3 +!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 wire_logic_cluster/lc_3/in_0 +!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_logic_cluster/lc_4/in_1 +!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_logic_cluster/lc_4/in_3 +!B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 wire_logic_cluster/lc_5/in_0 +!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_logic_cluster/lc_6/in_1 +!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_logic_cluster/lc_6/in_3 +!B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],!B1[33],!B1[34],!B1[35] buffer lc_trk_g0_4 input_2_0 +B4[35],B5[32],!B5[33],!B5[34],!B5[35] buffer lc_trk_g0_4 input_2_2 +B8[35],B9[32],!B9[33],!B9[34],!B9[35] buffer lc_trk_g0_4 input_2_4 +B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input_2_6 +B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 wire_logic_cluster/lc_0/in_0 +!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_logic_cluster/lc_1/in_3 +B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 wire_logic_cluster/lc_2/in_0 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_logic_cluster/lc_3/in_3 +B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 wire_logic_cluster/lc_4/in_0 +!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_logic_cluster/lc_5/in_3 +B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 wire_logic_cluster/lc_6/in_0 +!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_logic_cluster/lc_7/in_3 +!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_logic_cluster/lc_7/s_r +B2[35],B3[32],!B3[33],!B3[34],!B3[35] buffer lc_trk_g0_5 input_2_1 +B6[35],B7[32],!B7[33],!B7[34],!B7[35] buffer lc_trk_g0_5 input_2_3 +B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input_2_5 +B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input_2_7 +!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_logic_cluster/lc_0/in_3 +B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 wire_logic_cluster/lc_1/in_0 +!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_logic_cluster/lc_2/in_3 +B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 wire_logic_cluster/lc_3/in_0 +!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_logic_cluster/lc_4/in_3 +B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 wire_logic_cluster/lc_5/in_0 +!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_logic_cluster/lc_6/in_3 +B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],!B1[33],!B1[34],B1[35] buffer lc_trk_g0_6 input_2_0 +B4[35],B5[32],!B5[33],!B5[34],B5[35] buffer lc_trk_g0_6 input_2_2 +B8[35],B9[32],!B9[33],!B9[34],B9[35] buffer lc_trk_g0_6 input_2_4 +B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input_2_6 +B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 wire_logic_cluster/lc_0/in_0 +!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_logic_cluster/lc_1/in_3 +B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 wire_logic_cluster/lc_2/in_0 +!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_logic_cluster/lc_3/in_3 +B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 wire_logic_cluster/lc_4/in_0 +!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_logic_cluster/lc_5/in_3 +B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 wire_logic_cluster/lc_6/in_0 +!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_logic_cluster/lc_7/in_3 +B2[35],B3[32],!B3[33],!B3[34],B3[35] buffer lc_trk_g0_7 input_2_1 +B6[35],B7[32],!B7[33],!B7[34],B7[35] buffer lc_trk_g0_7 input_2_3 +B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input_2_5 +B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input_2_7 +!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_logic_cluster/lc_0/in_3 +B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 wire_logic_cluster/lc_1/in_0 +!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_logic_cluster/lc_2/in_3 +B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 wire_logic_cluster/lc_3/in_0 +!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_logic_cluster/lc_4/in_3 +B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 wire_logic_cluster/lc_5/in_0 +!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_logic_cluster/lc_6/in_3 +B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 wire_logic_cluster/lc_7/in_0 +!B2[35],B3[32],!B3[33],B3[34],!B3[35] buffer lc_trk_g1_0 input_2_1 +!B6[35],B7[32],!B7[33],B7[34],!B7[35] buffer lc_trk_g1_0 input_2_3 +!B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input_2_5 +!B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input_2_7 +B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_logic_cluster/lc_0/in_1 +!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_logic_cluster/lc_0/in_3 +!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 wire_logic_cluster/lc_1/in_0 +B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_logic_cluster/lc_2/in_1 +!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_logic_cluster/lc_2/in_3 +!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 wire_logic_cluster/lc_3/in_0 +B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_logic_cluster/lc_4/in_1 +!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_logic_cluster/lc_4/in_3 +!B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 wire_logic_cluster/lc_5/in_0 +B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_logic_cluster/lc_6/in_1 +!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_logic_cluster/lc_6/in_3 +!B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 wire_logic_cluster/lc_7/in_0 +!B0[35],B1[32],!B1[33],B1[34],!B1[35] buffer lc_trk_g1_1 input_2_0 +!B4[35],B5[32],!B5[33],B5[34],!B5[35] buffer lc_trk_g1_1 input_2_2 +!B8[35],B9[32],!B9[33],B9[34],!B9[35] buffer lc_trk_g1_1 input_2_4 +!B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input_2_6 +!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 wire_logic_cluster/lc_0/in_0 +B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_logic_cluster/lc_1/in_1 +!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_logic_cluster/lc_1/in_3 +!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 wire_logic_cluster/lc_2/in_0 +B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_logic_cluster/lc_3/in_1 +!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_logic_cluster/lc_3/in_3 +!B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 wire_logic_cluster/lc_4/in_0 +B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_logic_cluster/lc_5/in_1 +!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_logic_cluster/lc_5/in_3 +!B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 wire_logic_cluster/lc_6/in_0 +!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_logic_cluster/lc_7/clk +B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_logic_cluster/lc_7/in_1 +!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_logic_cluster/lc_7/in_3 +!B2[35],B3[32],!B3[33],B3[34],B3[35] buffer lc_trk_g1_2 input_2_1 +!B6[35],B7[32],!B7[33],B7[34],B7[35] buffer lc_trk_g1_2 input_2_3 +!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input_2_5 +!B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input_2_7 +B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_logic_cluster/lc_0/in_1 +!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_logic_cluster/lc_0/in_3 +!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 wire_logic_cluster/lc_1/in_0 +B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_logic_cluster/lc_2/in_1 +!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_logic_cluster/lc_2/in_3 +!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 wire_logic_cluster/lc_3/in_0 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_logic_cluster/lc_4/in_1 +!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_logic_cluster/lc_4/in_3 +!B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 wire_logic_cluster/lc_5/in_0 +B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_logic_cluster/lc_6/in_1 +!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_logic_cluster/lc_6/in_3 +!B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 wire_logic_cluster/lc_7/in_0 +!B0[35],B1[32],!B1[33],B1[34],B1[35] buffer lc_trk_g1_3 input_2_0 +!B4[35],B5[32],!B5[33],B5[34],B5[35] buffer lc_trk_g1_3 input_2_2 +!B8[35],B9[32],!B9[33],B9[34],B9[35] buffer lc_trk_g1_3 input_2_4 +!B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input_2_6 +!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 wire_logic_cluster/lc_0/in_0 +B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_logic_cluster/lc_1/in_1 +!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_logic_cluster/lc_1/in_3 +!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 wire_logic_cluster/lc_2/in_0 +B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_logic_cluster/lc_3/in_1 +!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_logic_cluster/lc_3/in_3 +!B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 wire_logic_cluster/lc_4/in_0 +B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_logic_cluster/lc_5/in_1 +!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_logic_cluster/lc_5/in_3 +!B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 wire_logic_cluster/lc_6/in_0 +!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_logic_cluster/lc_7/cen +B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_logic_cluster/lc_7/in_1 +!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_logic_cluster/lc_7/in_3 +B2[35],B3[32],!B3[33],B3[34],!B3[35] buffer lc_trk_g1_4 input_2_1 +B6[35],B7[32],!B7[33],B7[34],!B7[35] buffer lc_trk_g1_4 input_2_3 +B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input_2_5 +B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input_2_7 +B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_logic_cluster/lc_0/in_3 +B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 wire_logic_cluster/lc_1/in_0 +B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_logic_cluster/lc_2/in_3 +B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 wire_logic_cluster/lc_3/in_0 +B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_logic_cluster/lc_4/in_3 +B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 wire_logic_cluster/lc_5/in_0 +B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_logic_cluster/lc_6/in_3 +B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],!B1[33],B1[34],!B1[35] buffer lc_trk_g1_5 input_2_0 +B4[35],B5[32],!B5[33],B5[34],!B5[35] buffer lc_trk_g1_5 input_2_2 +B8[35],B9[32],!B9[33],B9[34],!B9[35] buffer lc_trk_g1_5 input_2_4 +B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input_2_6 +B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 wire_logic_cluster/lc_0/in_0 +B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_logic_cluster/lc_1/in_3 +B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 wire_logic_cluster/lc_2/in_0 +B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_logic_cluster/lc_3/in_3 +B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 wire_logic_cluster/lc_4/in_0 +B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_logic_cluster/lc_5/in_3 +B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 wire_logic_cluster/lc_6/in_0 +B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_logic_cluster/lc_7/in_3 +!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_logic_cluster/lc_7/s_r +B2[35],B3[32],!B3[33],B3[34],B3[35] buffer lc_trk_g1_6 input_2_1 +B6[35],B7[32],!B7[33],B7[34],B7[35] buffer lc_trk_g1_6 input_2_3 +B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input_2_5 +B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input_2_7 +B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_logic_cluster/lc_0/in_3 +B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 wire_logic_cluster/lc_1/in_0 +B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_logic_cluster/lc_2/in_3 +B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 wire_logic_cluster/lc_3/in_0 +B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_logic_cluster/lc_4/in_3 +B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 wire_logic_cluster/lc_5/in_0 +B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_logic_cluster/lc_6/in_3 +B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],!B1[33],B1[34],B1[35] buffer lc_trk_g1_7 input_2_0 +B4[35],B5[32],!B5[33],B5[34],B5[35] buffer lc_trk_g1_7 input_2_2 +B8[35],B9[32],!B9[33],B9[34],B9[35] buffer lc_trk_g1_7 input_2_4 +B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input_2_6 +B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 wire_logic_cluster/lc_0/in_0 +B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_logic_cluster/lc_1/in_3 +B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 wire_logic_cluster/lc_2/in_0 +B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_logic_cluster/lc_3/in_3 +B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 wire_logic_cluster/lc_4/in_0 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_logic_cluster/lc_5/in_3 +B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 wire_logic_cluster/lc_6/in_0 +B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_logic_cluster/lc_7/in_3 +!B0[35],B1[32],B1[33],!B1[34],!B1[35] buffer lc_trk_g2_0 input_2_0 +!B4[35],B5[32],B5[33],!B5[34],!B5[35] buffer lc_trk_g2_0 input_2_2 +!B8[35],B9[32],B9[33],!B9[34],!B9[35] buffer lc_trk_g2_0 input_2_4 +!B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input_2_6 +!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 wire_logic_cluster/lc_0/in_0 +!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_logic_cluster/lc_1/in_1 +!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_logic_cluster/lc_1/in_3 +!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 wire_logic_cluster/lc_2/in_0 +!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_logic_cluster/lc_3/in_1 +!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_logic_cluster/lc_3/in_3 +!B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 wire_logic_cluster/lc_4/in_0 +!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_logic_cluster/lc_5/in_1 +!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_logic_cluster/lc_5/in_3 +!B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 wire_logic_cluster/lc_6/in_0 +B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_logic_cluster/lc_7/clk +!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_logic_cluster/lc_7/in_1 +!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_logic_cluster/lc_7/in_3 +!B2[35],B3[32],B3[33],!B3[34],!B3[35] buffer lc_trk_g2_1 input_2_1 +!B6[35],B7[32],B7[33],!B7[34],!B7[35] buffer lc_trk_g2_1 input_2_3 +!B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input_2_5 +!B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input_2_7 +!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_logic_cluster/lc_0/in_1 +!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_logic_cluster/lc_0/in_3 +!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 wire_logic_cluster/lc_1/in_0 +!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_logic_cluster/lc_2/in_1 +!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_logic_cluster/lc_2/in_3 +!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 wire_logic_cluster/lc_3/in_0 +!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_logic_cluster/lc_4/in_1 +!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_logic_cluster/lc_4/in_3 +!B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 wire_logic_cluster/lc_5/in_0 +!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_logic_cluster/lc_6/in_1 +!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_logic_cluster/lc_6/in_3 +!B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 wire_logic_cluster/lc_7/in_0 +!B0[35],B1[32],B1[33],!B1[34],B1[35] buffer lc_trk_g2_2 input_2_0 +!B4[35],B5[32],B5[33],!B5[34],B5[35] buffer lc_trk_g2_2 input_2_2 +!B8[35],B9[32],B9[33],!B9[34],B9[35] buffer lc_trk_g2_2 input_2_4 +!B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input_2_6 +!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 wire_logic_cluster/lc_0/in_0 +!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_logic_cluster/lc_1/in_1 +!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_logic_cluster/lc_1/in_3 +!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 wire_logic_cluster/lc_2/in_0 +!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_logic_cluster/lc_3/in_1 +!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_logic_cluster/lc_3/in_3 +!B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 wire_logic_cluster/lc_4/in_0 +!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_logic_cluster/lc_5/in_1 +!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_logic_cluster/lc_5/in_3 +!B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 wire_logic_cluster/lc_6/in_0 +B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_logic_cluster/lc_7/cen +!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_logic_cluster/lc_7/in_1 +!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_logic_cluster/lc_7/in_3 +!B2[35],B3[32],B3[33],!B3[34],B3[35] buffer lc_trk_g2_3 input_2_1 +!B6[35],B7[32],B7[33],!B7[34],B7[35] buffer lc_trk_g2_3 input_2_3 +!B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input_2_5 +!B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input_2_7 +!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_logic_cluster/lc_0/in_1 +!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_logic_cluster/lc_0/in_3 +!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 wire_logic_cluster/lc_1/in_0 +!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_logic_cluster/lc_2/in_1 +!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_logic_cluster/lc_2/in_3 +!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 wire_logic_cluster/lc_3/in_0 +!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_logic_cluster/lc_4/in_1 +!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_logic_cluster/lc_4/in_3 +!B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 wire_logic_cluster/lc_5/in_0 +!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_logic_cluster/lc_6/in_1 +!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_logic_cluster/lc_6/in_3 +!B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],B1[33],!B1[34],!B1[35] buffer lc_trk_g2_4 input_2_0 +B4[35],B5[32],B5[33],!B5[34],!B5[35] buffer lc_trk_g2_4 input_2_2 +B8[35],B9[32],B9[33],!B9[34],!B9[35] buffer lc_trk_g2_4 input_2_4 +B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input_2_6 +B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 wire_logic_cluster/lc_0/in_0 +!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_logic_cluster/lc_1/in_3 +B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 wire_logic_cluster/lc_2/in_0 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_logic_cluster/lc_3/in_3 +B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 wire_logic_cluster/lc_4/in_0 +!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_logic_cluster/lc_5/in_3 +B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 wire_logic_cluster/lc_6/in_0 +!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_logic_cluster/lc_7/in_3 +B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_logic_cluster/lc_7/s_r +B2[35],B3[32],B3[33],!B3[34],!B3[35] buffer lc_trk_g2_5 input_2_1 +B6[35],B7[32],B7[33],!B7[34],!B7[35] buffer lc_trk_g2_5 input_2_3 +B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input_2_5 +B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input_2_7 +!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_logic_cluster/lc_0/in_3 +B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 wire_logic_cluster/lc_1/in_0 +!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_logic_cluster/lc_2/in_3 +B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 wire_logic_cluster/lc_3/in_0 +!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_logic_cluster/lc_4/in_3 +B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 wire_logic_cluster/lc_5/in_0 +!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_logic_cluster/lc_6/in_3 +B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],B1[33],!B1[34],B1[35] buffer lc_trk_g2_6 input_2_0 +B4[35],B5[32],B5[33],!B5[34],B5[35] buffer lc_trk_g2_6 input_2_2 +B8[35],B9[32],B9[33],!B9[34],B9[35] buffer lc_trk_g2_6 input_2_4 +B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input_2_6 +B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 wire_logic_cluster/lc_0/in_0 +!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_logic_cluster/lc_1/in_3 +B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 wire_logic_cluster/lc_2/in_0 +!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_logic_cluster/lc_3/in_3 +B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 wire_logic_cluster/lc_4/in_0 +!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_logic_cluster/lc_5/in_3 +B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 wire_logic_cluster/lc_6/in_0 +!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_logic_cluster/lc_7/in_3 +B2[35],B3[32],B3[33],!B3[34],B3[35] buffer lc_trk_g2_7 input_2_1 +B6[35],B7[32],B7[33],!B7[34],B7[35] buffer lc_trk_g2_7 input_2_3 +B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input_2_5 +B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input_2_7 +!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_logic_cluster/lc_0/in_3 +B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 wire_logic_cluster/lc_1/in_0 +!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_logic_cluster/lc_2/in_3 +B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 wire_logic_cluster/lc_3/in_0 +!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_logic_cluster/lc_4/in_3 +B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 wire_logic_cluster/lc_5/in_0 +!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_logic_cluster/lc_6/in_3 +B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 wire_logic_cluster/lc_7/in_0 +!B2[35],B3[32],B3[33],B3[34],!B3[35] buffer lc_trk_g3_0 input_2_1 +!B6[35],B7[32],B7[33],B7[34],!B7[35] buffer lc_trk_g3_0 input_2_3 +!B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input_2_5 +!B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input_2_7 +B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_logic_cluster/lc_0/in_1 +!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_logic_cluster/lc_0/in_3 +!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 wire_logic_cluster/lc_1/in_0 +B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_logic_cluster/lc_2/in_1 +!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_logic_cluster/lc_2/in_3 +!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 wire_logic_cluster/lc_3/in_0 +B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_logic_cluster/lc_4/in_1 +!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_logic_cluster/lc_4/in_3 +!B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 wire_logic_cluster/lc_5/in_0 +B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_logic_cluster/lc_6/in_1 +!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_logic_cluster/lc_6/in_3 +!B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 wire_logic_cluster/lc_7/in_0 +!B0[35],B1[32],B1[33],B1[34],!B1[35] buffer lc_trk_g3_1 input_2_0 +!B4[35],B5[32],B5[33],B5[34],!B5[35] buffer lc_trk_g3_1 input_2_2 +!B8[35],B9[32],B9[33],B9[34],!B9[35] buffer lc_trk_g3_1 input_2_4 +!B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input_2_6 +!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 wire_logic_cluster/lc_0/in_0 +B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_logic_cluster/lc_1/in_1 +!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_logic_cluster/lc_1/in_3 +!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 wire_logic_cluster/lc_2/in_0 +B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_logic_cluster/lc_3/in_1 +!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_logic_cluster/lc_3/in_3 +!B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 wire_logic_cluster/lc_4/in_0 +B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_logic_cluster/lc_5/in_1 +!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_logic_cluster/lc_5/in_3 +!B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 wire_logic_cluster/lc_6/in_0 +B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_logic_cluster/lc_7/clk +B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_logic_cluster/lc_7/in_1 +!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_logic_cluster/lc_7/in_3 +!B2[35],B3[32],B3[33],B3[34],B3[35] buffer lc_trk_g3_2 input_2_1 +!B6[35],B7[32],B7[33],B7[34],B7[35] buffer lc_trk_g3_2 input_2_3 +!B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input_2_5 +!B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input_2_7 +B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_logic_cluster/lc_0/in_1 +!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_logic_cluster/lc_0/in_3 +!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 wire_logic_cluster/lc_1/in_0 +B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_logic_cluster/lc_2/in_1 +!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_logic_cluster/lc_2/in_3 +!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 wire_logic_cluster/lc_3/in_0 +B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_logic_cluster/lc_4/in_1 +!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_logic_cluster/lc_4/in_3 +!B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 wire_logic_cluster/lc_5/in_0 +B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_logic_cluster/lc_6/in_1 +!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_logic_cluster/lc_6/in_3 +!B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 wire_logic_cluster/lc_7/in_0 +!B0[35],B1[32],B1[33],B1[34],B1[35] buffer lc_trk_g3_3 input_2_0 +!B4[35],B5[32],B5[33],B5[34],B5[35] buffer lc_trk_g3_3 input_2_2 +!B8[35],B9[32],B9[33],B9[34],B9[35] buffer lc_trk_g3_3 input_2_4 +!B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input_2_6 +!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 wire_logic_cluster/lc_0/in_0 +B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_logic_cluster/lc_1/in_1 +!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_logic_cluster/lc_1/in_3 +!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 wire_logic_cluster/lc_2/in_0 +B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_logic_cluster/lc_3/in_1 +!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_logic_cluster/lc_3/in_3 +!B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 wire_logic_cluster/lc_4/in_0 +B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_logic_cluster/lc_5/in_1 +!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_logic_cluster/lc_5/in_3 +!B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 wire_logic_cluster/lc_6/in_0 +B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_logic_cluster/lc_7/cen +B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_logic_cluster/lc_7/in_1 +!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_logic_cluster/lc_7/in_3 +B2[35],B3[32],B3[33],B3[34],!B3[35] buffer lc_trk_g3_4 input_2_1 +B6[35],B7[32],B7[33],B7[34],!B7[35] buffer lc_trk_g3_4 input_2_3 +B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input_2_5 +B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input_2_7 +B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_logic_cluster/lc_0/in_3 +B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 wire_logic_cluster/lc_1/in_0 +B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_logic_cluster/lc_2/in_3 +B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 wire_logic_cluster/lc_3/in_0 +B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_logic_cluster/lc_4/in_3 +B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 wire_logic_cluster/lc_5/in_0 +B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_logic_cluster/lc_6/in_3 +B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],B1[33],B1[34],!B1[35] buffer lc_trk_g3_5 input_2_0 +B4[35],B5[32],B5[33],B5[34],!B5[35] buffer lc_trk_g3_5 input_2_2 +B8[35],B9[32],B9[33],B9[34],!B9[35] buffer lc_trk_g3_5 input_2_4 +B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input_2_6 +B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 wire_logic_cluster/lc_0/in_0 +B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_logic_cluster/lc_1/in_3 +B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 wire_logic_cluster/lc_2/in_0 +B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_logic_cluster/lc_3/in_3 +B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 wire_logic_cluster/lc_4/in_0 +B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_logic_cluster/lc_5/in_3 +B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 wire_logic_cluster/lc_6/in_0 +B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_logic_cluster/lc_7/in_3 +B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_logic_cluster/lc_7/s_r +B2[35],B3[32],B3[33],B3[34],B3[35] buffer lc_trk_g3_6 input_2_1 +B6[35],B7[32],B7[33],B7[34],B7[35] buffer lc_trk_g3_6 input_2_3 +B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input_2_5 +B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input_2_7 +B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_logic_cluster/lc_0/in_3 +B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 wire_logic_cluster/lc_1/in_0 +B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_logic_cluster/lc_2/in_3 +B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 wire_logic_cluster/lc_3/in_0 +B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_logic_cluster/lc_4/in_3 +B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 wire_logic_cluster/lc_5/in_0 +B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_logic_cluster/lc_6/in_3 +B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],B1[33],B1[34],B1[35] buffer lc_trk_g3_7 input_2_0 +B4[35],B5[32],B5[33],B5[34],B5[35] buffer lc_trk_g3_7 input_2_2 +B8[35],B9[32],B9[33],B9[34],B9[35] buffer lc_trk_g3_7 input_2_4 +B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input_2_6 +B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 wire_logic_cluster/lc_0/in_0 +B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_logic_cluster/lc_1/in_3 +B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 wire_logic_cluster/lc_2/in_0 +B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_logic_cluster/lc_3/in_3 +B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 wire_logic_cluster/lc_4/in_0 +B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_logic_cluster/lc_5/in_3 +B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 wire_logic_cluster/lc_6/in_0 +B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_logic_cluster/lc_7/in_3 +B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 +B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 +B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 +B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 +B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 +B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 +B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 +B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 +B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 +!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 +!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 +!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 +!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 +B10[2] buffer sp12_h_l_17 sp4_h_r_21 +!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5 +!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6 +B14[2] buffer sp12_h_l_21 sp4_h_l_10 +B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 +B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 +B15[19] buffer sp12_h_l_3 sp4_h_r_14 +B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7 +B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 +B14[19] buffer sp12_h_l_5 sp4_h_l_2 +B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 +B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 +B13[19] buffer sp12_h_r_0 sp4_h_l_1 +B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 +!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2 +B3[1] buffer sp12_h_r_10 sp4_h_l_4 +!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 +!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 +!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 +B4[2] buffer sp12_h_r_12 sp4_h_l_7 +!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5 +!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 +B6[2] buffer sp12_h_r_14 sp4_h_r_19 +!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0 +B8[2] buffer sp12_h_r_16 sp4_h_l_9 +B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 +B12[19] buffer sp12_h_r_2 sp4_h_r_13 +!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 +B12[2] buffer sp12_h_r_20 sp4_h_l_11 +!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7 +B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3 +B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 +!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 +!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 +B0[2] buffer sp12_h_r_8 sp4_h_l_5 +!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 +B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 +B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 +B1[19] buffer sp12_v_b_1 sp4_v_t_1 +!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 +B4[19] buffer sp12_v_b_11 sp4_v_b_17 +!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 +!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 +!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 +!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 +!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 +!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_b_18 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_b_18 lc_trk_g3_2 +!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3 +B8[19] buffer sp12_v_b_19 sp4_v_b_21 +!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4 +!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 +!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5 +B11[19] buffer sp12_v_b_21 sp4_v_b_22 +!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 +B10[19] buffer sp12_v_b_23 sp4_v_b_23 +B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_b_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_b_7 lc_trk_g3_7 +B2[19] buffer sp12_v_b_7 sp4_v_b_15 +!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_8 lc_trk_g2_0 +!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_8 lc_trk_g3_0 +B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_t_0 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_t_0 lc_trk_g3_3 +B0[19] buffer sp12_v_t_0 sp4_v_b_13 +B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_t_1 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_t_1 lc_trk_g3_2 +!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5 +B7[19] buffer sp12_v_t_10 sp4_v_b_18 +!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 +B6[19] buffer sp12_v_t_12 sp4_v_b_19 +!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 +B9[19] buffer sp12_v_t_14 sp4_v_t_9 +B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_t_2 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_t_2 lc_trk_g3_5 +B3[19] buffer sp12_v_t_2 sp4_v_t_3 +!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 +B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 +B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4 +!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_t_6 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_t_6 lc_trk_g3_1 +B5[19] buffer sp12_v_t_6 sp4_v_t_5 +!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2 +B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4 +B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_1 lc_trk_g1_4 +B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 +B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 +!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 +B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 +!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4 +!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4 +B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 +B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 +B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0 +B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_l_24 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_l_24 lc_trk_g3_5 +B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_34 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_34 lc_trk_g3_7 +B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_l_4 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_l_4 lc_trk_g1_1 +B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_l_5 lc_trk_g0_0 +B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_l_5 lc_trk_g1_0 +B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2 +B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 +B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 +!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 +!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 +B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 +B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_r_14 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_r_14 lc_trk_g1_6 +B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 +!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 +B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 +!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0 +!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0 +B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 +!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 +!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 +!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 +!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_31 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7 +B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1 +B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 +B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3 +B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 +B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 +B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_r_38 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_r_38 lc_trk_g3_6 +B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_r_39 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_r_39 lc_trk_g3_7 +!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 +!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 +B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 +B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 +B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_r_41 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_r_41 lc_trk_g3_1 +B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 +B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3 +B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 +B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 +B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 +B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 +B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 +!B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 +!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 +B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 +B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 +B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 +!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 +!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 +!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 +!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 +!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 +!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 +!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 +!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 +!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 +!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 +!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 +!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 +!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 +!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 +!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 +!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 +!B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 +!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 +!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 +!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 +!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 +!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 +!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 +!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 +!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 +!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 +!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 +!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 +!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 +!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 +!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 +!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 +!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 +!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 +B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 +B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 +!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 +B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_b_15 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_b_15 lc_trk_g1_7 +B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1 +!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_b_18 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_b_18 lc_trk_g1_2 +!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3 +B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 +B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_b_21 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_b_21 lc_trk_g1_5 +!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_b_22 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_b_22 lc_trk_g1_6 +!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_b_23 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_b_23 lc_trk_g1_7 +B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_24 lc_trk_g2_0 +B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_24 lc_trk_g3_0 +B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_b_26 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_b_26 lc_trk_g3_2 +B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 +B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6 +!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1 +B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_36 lc_trk_g2_4 +B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_36 lc_trk_g3_4 +!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5 +B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6 +B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 +B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 +!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_b_42 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_b_42 lc_trk_g3_2 +!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 +!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_b_47 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_b_47 lc_trk_g3_7 +!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 +B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 +B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 +B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 +B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 +B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4 +B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4 +!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_t_12 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_t_12 lc_trk_g3_1 +B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_t_14 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_t_14 lc_trk_g3_3 +!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_t_16 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_t_16 lc_trk_g3_5 +B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_17 lc_trk_g2_4 +B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_17 lc_trk_g3_4 +B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7 +B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0 +B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0 +B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3 +B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 +B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 +B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_t_28 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_t_28 lc_trk_g3_1 +!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_t_29 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_t_29 lc_trk_g3_0 +B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_t_3 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_t_3 lc_trk_g1_6 +!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3 +B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_t_32 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_t_32 lc_trk_g3_5 +!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4 +!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_t_5 lc_trk_g0_0 +!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_t_5 lc_trk_g1_0 +!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_t_9 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_t_9 lc_trk_g1_4 +!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 +!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 +!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 +!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 +!B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 +!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 +!B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 +!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 +!B0[14],B1[14],B1[15],!B1[16],B1[17] buffer top_op_0 lc_trk_g0_0 +!B4[14],B5[14],B5[15],!B5[16],B5[17] buffer top_op_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer top_op_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer top_op_1 lc_trk_g1_1 +!B0[25],B1[22],!B1[23],B1[24],B1[25] buffer top_op_2 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2 +!B0[21],B0[22],!B0[23],B0[24],B1[21] buffer top_op_3 lc_trk_g0_3 +!B4[21],B4[22],!B4[23],B4[24],B5[21] buffer top_op_3 lc_trk_g1_3 +!B2[14],B3[14],B3[15],!B3[16],B3[17] buffer top_op_4 lc_trk_g0_4 +!B6[14],B7[14],B7[15],!B7[16],B7[17] buffer top_op_4 lc_trk_g1_4 +B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer top_op_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer top_op_5 lc_trk_g1_5 +!B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],B7[24],B7[25] buffer top_op_6 lc_trk_g1_6 +!B2[21],B2[22],!B2[23],B2[24],B3[21] buffer top_op_7 lc_trk_g0_7 +!B6[21],B6[22],!B6[23],B6[24],B7[21] buffer top_op_7 lc_trk_g1_7 +!B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer wire_logic_cluster/carry_in_mux/cout wire_logic_cluster/lc_0/in_3 +!B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer wire_logic_cluster/lc_0/cout wire_logic_cluster/lc_1/in_3 +B2[50] buffer wire_logic_cluster/lc_0/out input_2_1 +B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer wire_logic_cluster/lc_0/out lc_trk_g0_0 +B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer wire_logic_cluster/lc_0/out lc_trk_g1_0 +B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer wire_logic_cluster/lc_0/out lc_trk_g2_0 +B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer wire_logic_cluster/lc_0/out lc_trk_g3_0 +B0[47] buffer wire_logic_cluster/lc_0/out sp12_h_r_8 +B0[51] buffer wire_logic_cluster/lc_0/out sp12_v_b_0 +B0[52] buffer wire_logic_cluster/lc_0/out sp12_v_b_16 +B1[47] buffer wire_logic_cluster/lc_0/out sp4_h_l_21 +B0[46] buffer wire_logic_cluster/lc_0/out sp4_h_l_5 +B1[46] buffer wire_logic_cluster/lc_0/out sp4_h_r_0 +B1[52] buffer wire_logic_cluster/lc_0/out sp4_r_v_b_1 +B0[53] buffer wire_logic_cluster/lc_0/out sp4_r_v_b_17 +B1[53] buffer wire_logic_cluster/lc_0/out sp4_r_v_b_33 +B0[48] buffer wire_logic_cluster/lc_0/out sp4_v_b_0 +B1[51] buffer wire_logic_cluster/lc_0/out sp4_v_t_21 +B1[48] buffer wire_logic_cluster/lc_0/out sp4_v_t_5 +!B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer wire_logic_cluster/lc_1/cout wire_logic_cluster/lc_2/in_3 +B4[50] buffer wire_logic_cluster/lc_1/out input_2_2 +!B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer wire_logic_cluster/lc_1/out lc_trk_g0_1 +!B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer wire_logic_cluster/lc_1/out lc_trk_g1_1 +!B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer wire_logic_cluster/lc_1/out lc_trk_g2_1 +!B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer wire_logic_cluster/lc_1/out lc_trk_g3_1 +B2[47] buffer wire_logic_cluster/lc_1/out sp12_h_r_10 +B2[52] buffer wire_logic_cluster/lc_1/out sp12_v_b_18 +B2[51] buffer wire_logic_cluster/lc_1/out sp12_v_t_1 +B2[46] buffer wire_logic_cluster/lc_1/out sp4_h_l_7 +B3[46] buffer wire_logic_cluster/lc_1/out sp4_h_r_2 +B3[47] buffer wire_logic_cluster/lc_1/out sp4_h_r_34 +B2[53] buffer wire_logic_cluster/lc_1/out sp4_r_v_b_19 +B3[52] buffer wire_logic_cluster/lc_1/out sp4_r_v_b_3 +B3[53] buffer wire_logic_cluster/lc_1/out sp4_r_v_b_35 +B3[48] buffer wire_logic_cluster/lc_1/out sp4_v_b_18 +B2[48] buffer wire_logic_cluster/lc_1/out sp4_v_b_2 +B3[51] buffer wire_logic_cluster/lc_1/out sp4_v_t_23 +!B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer wire_logic_cluster/lc_2/cout wire_logic_cluster/lc_3/in_3 +B6[50] buffer wire_logic_cluster/lc_2/out input_2_3 +B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer wire_logic_cluster/lc_2/out lc_trk_g0_2 +B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer wire_logic_cluster/lc_2/out lc_trk_g1_2 +B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer wire_logic_cluster/lc_2/out lc_trk_g2_2 +B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer wire_logic_cluster/lc_2/out lc_trk_g3_2 +B4[47] buffer wire_logic_cluster/lc_2/out sp12_h_r_12 +B4[52] buffer wire_logic_cluster/lc_2/out sp12_v_b_20 +B4[51] buffer wire_logic_cluster/lc_2/out sp12_v_t_3 +B4[46] buffer wire_logic_cluster/lc_2/out sp4_h_l_9 +B5[47] buffer wire_logic_cluster/lc_2/out sp4_h_r_36 +B5[46] buffer wire_logic_cluster/lc_2/out sp4_h_r_4 +B4[53] buffer wire_logic_cluster/lc_2/out sp4_r_v_b_21 +B5[53] buffer wire_logic_cluster/lc_2/out sp4_r_v_b_37 +B5[52] buffer wire_logic_cluster/lc_2/out sp4_r_v_b_5 +B5[51] buffer wire_logic_cluster/lc_2/out sp4_v_b_36 +B4[48] buffer wire_logic_cluster/lc_2/out sp4_v_b_4 +B5[48] buffer wire_logic_cluster/lc_2/out sp4_v_t_9 +!B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer wire_logic_cluster/lc_3/cout wire_logic_cluster/lc_4/in_3 +B8[50] buffer wire_logic_cluster/lc_3/out input_2_4 +B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer wire_logic_cluster/lc_3/out lc_trk_g0_3 +B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer wire_logic_cluster/lc_3/out lc_trk_g1_3 +B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer wire_logic_cluster/lc_3/out lc_trk_g2_3 +B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer wire_logic_cluster/lc_3/out lc_trk_g3_3 +B6[47] buffer wire_logic_cluster/lc_3/out sp12_h_r_14 +B6[51] buffer wire_logic_cluster/lc_3/out sp12_v_b_6 +B6[52] buffer wire_logic_cluster/lc_3/out sp12_v_t_21 +B6[46] buffer wire_logic_cluster/lc_3/out sp4_h_l_11 +B7[47] buffer wire_logic_cluster/lc_3/out sp4_h_r_38 +B7[46] buffer wire_logic_cluster/lc_3/out sp4_h_r_6 +B6[53] buffer wire_logic_cluster/lc_3/out sp4_r_v_b_23 +B7[53] buffer wire_logic_cluster/lc_3/out sp4_r_v_b_39 +B7[52] buffer wire_logic_cluster/lc_3/out sp4_r_v_b_7 +B7[48] buffer wire_logic_cluster/lc_3/out sp4_v_b_22 +B7[51] buffer wire_logic_cluster/lc_3/out sp4_v_b_38 +B6[48] buffer wire_logic_cluster/lc_3/out sp4_v_b_6 +!B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer wire_logic_cluster/lc_4/cout wire_logic_cluster/lc_5/in_3 +B10[50] buffer wire_logic_cluster/lc_4/out input_2_5 +B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer wire_logic_cluster/lc_4/out lc_trk_g0_4 +B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer wire_logic_cluster/lc_4/out lc_trk_g1_4 +B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer wire_logic_cluster/lc_4/out lc_trk_g2_4 +B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer wire_logic_cluster/lc_4/out lc_trk_g3_4 +B8[47] buffer wire_logic_cluster/lc_4/out sp12_h_r_0 +B8[48] buffer wire_logic_cluster/lc_4/out sp12_h_r_16 +B8[52] buffer wire_logic_cluster/lc_4/out sp12_v_b_8 +B8[46] buffer wire_logic_cluster/lc_4/out sp4_h_r_24 +B9[47] buffer wire_logic_cluster/lc_4/out sp4_h_r_40 +B9[46] buffer wire_logic_cluster/lc_4/out sp4_h_r_8 +B8[53] buffer wire_logic_cluster/lc_4/out sp4_r_v_b_25 +B9[53] buffer wire_logic_cluster/lc_4/out sp4_r_v_b_41 +B9[52] buffer wire_logic_cluster/lc_4/out sp4_r_v_b_9 +B9[51] buffer wire_logic_cluster/lc_4/out sp4_v_b_24 +B9[48] buffer wire_logic_cluster/lc_4/out sp4_v_b_8 +B8[51] buffer wire_logic_cluster/lc_4/out sp4_v_t_29 +!B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer wire_logic_cluster/lc_5/cout wire_logic_cluster/lc_6/in_3 +B12[50] buffer wire_logic_cluster/lc_5/out input_2_6 +!B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer wire_logic_cluster/lc_5/out lc_trk_g0_5 +!B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer wire_logic_cluster/lc_5/out lc_trk_g1_5 +!B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer wire_logic_cluster/lc_5/out lc_trk_g2_5 +!B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer wire_logic_cluster/lc_5/out lc_trk_g3_5 +B10[48] buffer wire_logic_cluster/lc_5/out sp12_h_l_17 +B10[47] buffer wire_logic_cluster/lc_5/out sp12_h_r_2 +B10[52] buffer wire_logic_cluster/lc_5/out sp12_v_t_9 +B10[46] buffer wire_logic_cluster/lc_5/out sp4_h_l_15 +B11[46] buffer wire_logic_cluster/lc_5/out sp4_h_r_10 +B11[47] buffer wire_logic_cluster/lc_5/out sp4_h_r_42 +B11[52] buffer wire_logic_cluster/lc_5/out sp4_r_v_b_11 +B10[53] buffer wire_logic_cluster/lc_5/out sp4_r_v_b_27 +B11[53] buffer wire_logic_cluster/lc_5/out sp4_r_v_b_43 +B11[48] buffer wire_logic_cluster/lc_5/out sp4_v_b_10 +B11[51] buffer wire_logic_cluster/lc_5/out sp4_v_b_26 +B10[51] buffer wire_logic_cluster/lc_5/out sp4_v_b_42 +!B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer wire_logic_cluster/lc_6/cout wire_logic_cluster/lc_7/in_3 +B14[50] buffer wire_logic_cluster/lc_6/out input_2_7 +B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer wire_logic_cluster/lc_6/out lc_trk_g0_6 +B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer wire_logic_cluster/lc_6/out lc_trk_g1_6 +B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer wire_logic_cluster/lc_6/out lc_trk_g2_6 +B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer wire_logic_cluster/lc_6/out lc_trk_g3_6 +B12[47] buffer wire_logic_cluster/lc_6/out sp12_h_l_3 +B12[48] buffer wire_logic_cluster/lc_6/out sp12_h_r_20 +B12[52] buffer wire_logic_cluster/lc_6/out sp12_v_b_12 +B13[46] buffer wire_logic_cluster/lc_6/out sp4_h_l_1 +B12[46] buffer wire_logic_cluster/lc_6/out sp4_h_l_17 +B13[47] buffer wire_logic_cluster/lc_6/out sp4_h_r_44 +B13[52] buffer wire_logic_cluster/lc_6/out sp4_r_v_b_13 +B12[53] buffer wire_logic_cluster/lc_6/out sp4_r_v_b_29 +B13[53] buffer wire_logic_cluster/lc_6/out sp4_r_v_b_45 +B13[48] buffer wire_logic_cluster/lc_6/out sp4_v_t_1 +B13[51] buffer wire_logic_cluster/lc_6/out sp4_v_t_17 +B12[51] buffer wire_logic_cluster/lc_6/out sp4_v_t_33 +B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer wire_logic_cluster/lc_7/out lc_trk_g0_7 +B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer wire_logic_cluster/lc_7/out lc_trk_g1_7 +B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer wire_logic_cluster/lc_7/out lc_trk_g2_7 +B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer wire_logic_cluster/lc_7/out lc_trk_g3_7 +B14[48] buffer wire_logic_cluster/lc_7/out sp12_h_l_21 +B14[47] buffer wire_logic_cluster/lc_7/out sp12_h_l_5 +B14[52] buffer wire_logic_cluster/lc_7/out sp12_v_b_14 +B15[46] buffer wire_logic_cluster/lc_7/out sp4_h_r_14 +B14[46] buffer wire_logic_cluster/lc_7/out sp4_h_r_30 +B15[47] buffer wire_logic_cluster/lc_7/out sp4_h_r_46 +B15[52] buffer wire_logic_cluster/lc_7/out sp4_r_v_b_15 +B14[53] buffer wire_logic_cluster/lc_7/out sp4_r_v_b_31 +B15[53] buffer wire_logic_cluster/lc_7/out sp4_r_v_b_47 +B15[51] buffer wire_logic_cluster/lc_7/out sp4_v_b_30 +B14[51] buffer wire_logic_cluster/lc_7/out sp4_v_b_46 +B15[48] buffer wire_logic_cluster/lc_7/out sp4_v_t_3 +!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 +!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 +!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 +!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 +!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 +!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 +B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 +B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 +B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 +B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 +B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 +B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 +!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 +B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 +B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 +!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 +B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 +B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 +B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 +B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 +B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 +B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 +B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 +B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 +B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 +!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 +!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 +B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 +B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 +B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 +!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 +!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 +B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 +!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 +B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 +B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 +!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 +B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 +!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 +!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 +B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 +B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 +B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 +!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 +B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 +B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 +!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 +B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 +!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 +B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 +!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 +!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 +B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 +!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 +B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 +B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 +!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 +!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 +!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 +!B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 +B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 +!B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 +B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 +B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 +B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 +!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 +!B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 +!B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 +B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 +B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 +B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 +!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 +B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 +!B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 +!B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 +B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 +B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 +B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 +!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 +B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 +B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 +!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 +!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 +B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 +B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 +B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 +!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 +B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 +B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 +!B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 +B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 +!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 +!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 +!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 +!B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 +B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 +B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 +!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 +B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 +!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 +!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 +!B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 +B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 +!B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 +B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 +B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 +!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 +B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 +!B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 +B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 +!B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 +!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 +B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 +B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 +B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 +B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 +!B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 +!B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 +B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 +!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 +B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 +B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 +!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 +!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 +B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 +B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 +!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 +B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 +B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 +B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 +B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 +!B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 +!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 +!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 +B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 +!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 +!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 +B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 +B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 +!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 +!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 +!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 +B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 +!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 +B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 +!B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 +!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 +B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 +B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 +B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 +!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 +B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 +!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 +B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 +!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 +B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 +B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 +B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 +!B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 +B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 +!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 +!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 +!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 +B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 +!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 +!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 +B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 +B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 +!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 +B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 +B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 +!B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 +B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 +!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 +!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 +B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 +B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 +B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 +B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 +!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 +B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 +!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 +!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 +B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 +!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 +B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 +!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 +!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 +B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 +!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 +B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 +B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 +B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 +!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 +B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 +B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 +B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 +!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 +B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 +!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 +!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 +B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 +B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 +!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 +B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 +B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 +!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 +!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 +B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 +B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 +B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 +B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 +!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 +!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 +B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 +B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 +B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 +B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 +!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 +!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 +B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 +!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 +B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 +B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 +!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 +B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 +!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 +B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 +!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 +B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 +B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 +B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 +!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 +B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 +!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 +!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 +B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 +B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 +B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 +!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 +B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 +B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 +!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 +B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 +B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 +!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 +!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 +B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 +B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 +!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 +B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 +B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 +B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 +B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 +!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 +!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 +!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 +B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 +B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 +B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 +!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 +B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 +!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 +B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 +B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 +B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 +!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 +!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 +B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 +!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 +B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 +B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 +B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 +!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 +B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 +B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 +B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 +B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 +!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 +!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 +!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 +B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 +B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 +B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 +B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 +B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 +!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 +B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 +!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 +B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 +B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 +B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 +B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 +!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 +B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 +B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 +!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 +B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 +B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 +B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 +!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 +!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 +!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 +B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 +B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 +B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 +!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 +B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 +!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 +!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 +B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 +B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 +B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 +!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 +!B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 +B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 +!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 +B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 +B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 +B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 +!B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 +!B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 +B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 +B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 +!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 +B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 +B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 +!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 +B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 +B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 +B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 +!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 +B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 +B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 +!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 +B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 +!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 +B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 +B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 +B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 +B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 +!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 +B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 +B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 +!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 +!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 +B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 +B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 +B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 +!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 +!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 +B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 +!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 +B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 +B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 +!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 +!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 +B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 +!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 +B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 +""" +database_ram_txt = """ +B6[7] Cascade MEMT_LC00_inmux00_bram_cbit_7 +B4[7] Cascade MEMT_LC01_inmux00_bram_cbit_5 +B7[7] Cascade MEMT_LC01_inmux00_bram_cbit_6 +B6[7] Cascade MEMT_LC01_inmux00_bram_cbit_7 +B5[7] Cascade MEMT_LC02_inmux00_bram_cbit_4 +B4[7] Cascade MEMT_LC02_inmux00_bram_cbit_5 +B5[7] Cascade MEMT_LC03_inmux00_bram_cbit_4 +B4[7] Cascade MEMT_LC03_inmux00_bram_cbit_5 +B7[7] Cascade MEMT_LC03_inmux00_bram_cbit_6 +B6[7] Cascade MEMT_LC03_inmux00_bram_cbit_7 +B5[7] Cascade MEMT_LC04_inmux00_bram_cbit_4 +B4[7] Cascade MEMT_LC04_inmux00_bram_cbit_5 +B7[7] Cascade MEMT_LC04_inmux00_bram_cbit_6 +B6[7] Cascade MEMT_LC04_inmux00_bram_cbit_7 +B7[7] Cascade MEMT_LC05_inmux00_bram_cbit_6 +B6[7] Cascade MEMT_LC05_inmux00_bram_cbit_7 +B5[7] Cascade MEMT_LC07_inmux00_bram_cbit_4 +B4[7] Cascade MEMT_LC07_inmux00_bram_cbit_5 +B0[1] ColBufCtrl MEMB_colbuf_cntl_0 B0[1] +B1[2] ColBufCtrl MEMB_colbuf_cntl_1 B1[2] +B11[7] ColBufCtrl MEMB_colbuf_cntl_2 B11[7] +B5[2] ColBufCtrl MEMB_colbuf_cntl_2 B5[2] +B7[2] ColBufCtrl MEMB_colbuf_cntl_3 B7[2] +B13[7] ColBufCtrl MEMB_colbuf_cntl_4 B13[7] +B9[2] ColBufCtrl MEMB_colbuf_cntl_4 B9[2] +B11[2] ColBufCtrl MEMB_colbuf_cntl_5 B11[2] +B13[2] ColBufCtrl MEMB_colbuf_cntl_6 B13[2] +B15[2] ColBufCtrl MEMB_colbuf_cntl_7 B15[2] +B11[7] ColBufCtrl MEMT_colbuf_cntl_2 B11[7] +B1[7] RamConfig MEMB_Power_Up_Control +B12[19] buffer sp12_h_l_1 sp4_h_r_13 +B6[2] buffer sp12_h_l_13 sp4_h_r_19 +B8[2] buffer sp12_h_l_15 sp4_h_l_9 +B10[2] buffer sp12_h_l_17 sp4_h_r_21 +B14[2] buffer sp12_h_l_21 sp4_h_l_10 +B15[19] buffer sp12_h_l_3 sp4_h_l_3 +B14[19] buffer sp12_h_l_5 sp4_h_l_2 +B14[19] buffer sp12_h_l_5 sp4_h_r_15 +B3[1] buffer sp12_h_l_9 sp4_h_r_17 +B13[19] buffer sp12_h_r_0 sp4_h_l_1 +B13[19] buffer sp12_h_r_0 sp4_h_r_12 +B3[1] buffer sp12_h_r_10 sp4_h_r_17 +B4[2] buffer sp12_h_r_12 sp4_h_l_7 +B4[2] buffer sp12_h_r_12 sp4_h_r_18 +B6[2] buffer sp12_h_r_14 sp4_h_l_6 +B8[2] buffer sp12_h_r_16 sp4_h_r_20 +B10[2] buffer sp12_h_r_18 sp4_h_l_8 +B12[19] buffer sp12_h_r_2 sp4_h_r_13 +B12[2] buffer sp12_h_r_20 sp4_h_l_11 +B12[2] buffer sp12_h_r_20 sp4_h_r_22 +B14[2] buffer sp12_h_r_22 sp4_h_r_23 +B0[2] buffer sp12_h_r_8 sp4_h_l_5 +B0[2] buffer sp12_h_r_8 sp4_h_r_16 +B1[19] buffer sp12_v_b_1 sp4_v_b_12 +B1[19] buffer sp12_v_b_1 sp4_v_t_1 +B4[19] buffer sp12_v_b_11 sp4_v_b_17 +B7[19] buffer sp12_v_b_13 sp4_v_t_7 +B9[19] buffer sp12_v_b_17 sp4_v_b_20 +B8[19] buffer sp12_v_b_19 sp4_v_t_8 +B11[19] buffer sp12_v_b_21 sp4_v_b_22 +B10[19] buffer sp12_v_b_23 sp4_v_t_10 +B0[19] buffer sp12_v_b_3 sp4_v_b_13 +B3[19] buffer sp12_v_b_5 sp4_v_b_14 +B2[19] buffer sp12_v_b_7 sp4_v_t_2 +B5[19] buffer sp12_v_b_9 sp4_v_b_16 +B0[19] buffer sp12_v_t_0 sp4_v_b_13 +B7[19] buffer sp12_v_t_10 sp4_v_t_7 +B6[19] buffer sp12_v_t_12 sp4_v_b_19 +B6[19] buffer sp12_v_t_12 sp4_v_t_6 +B9[19] buffer sp12_v_t_14 sp4_v_b_20 +B8[19] buffer sp12_v_t_16 sp4_v_t_8 +B11[19] buffer sp12_v_t_18 sp4_v_t_11 +B10[19] buffer sp12_v_t_20 sp4_v_b_23 +B2[19] buffer sp12_v_t_4 sp4_v_t_2 +B4[19] buffer sp12_v_t_8 sp4_v_t_4 +!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 +!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 +!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 +!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 +!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 +!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 +B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 +B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 +B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 +B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 +B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 +B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 +!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 +B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 +B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 +!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 +B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 +B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 +B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 +B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 +B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 +B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 +B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 +B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 +B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 +!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 +!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 +B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 +B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 +B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 +!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 +!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 +B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 +!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 +B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 +B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 +!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 +B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 +!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 +!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 +B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 +B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 +B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 +!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 +B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 +B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 +!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 +B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 +!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 +B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 +!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 +!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 +B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 +!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 +B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 +B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 +!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 +!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 +!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 +!B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 +B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 +!B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 +B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 +B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 +B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 +!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 +!B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 +!B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 +B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 +B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 +B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 +!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 +B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 +!B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 +!B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 +B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 +B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 +B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 +!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 +B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 +B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 +!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 +!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 +B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 +B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 +B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 +!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 +B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 +B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 +!B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 +B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 +!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 +!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 +!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 +!B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 +B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 +B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 +!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 +B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 +!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 +!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 +!B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 +B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 +!B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 +B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 +B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 +!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 +B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 +!B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 +B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 +!B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 +!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 +B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 +B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 +B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 +B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 +!B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 +!B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 +B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 +!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 +B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 +B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 +!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 +!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 +B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 +B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 +!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 +B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 +B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 +B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 +B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 +!B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 +!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 +!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 +B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 +!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 +!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 +B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 +B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 +!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 +!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 +!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 +B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 +!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 +B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 +!B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 +!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 +B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 +B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 +B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 +!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 +B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 +!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 +B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 +!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 +B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 +B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 +B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 +!B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 +B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 +!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 +!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 +!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 +B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 +!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 +!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 +B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 +B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 +!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 +B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 +B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 +!B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 +B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 +!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 +!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 +B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 +B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 +B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 +B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 +!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 +B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 +!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 +!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 +B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 +!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 +B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 +!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 +!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 +B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 +!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 +B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 +B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 +B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 +!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 +B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 +B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 +B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 +!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 +B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 +!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 +!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 +B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 +B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 +!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 +B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 +B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 +!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 +!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 +B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 +B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 +B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 +B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 +!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 +!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 +B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 +B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 +B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 +B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 +!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 +!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 +B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 +!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 +B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 +B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 +!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 +B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 +!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 +B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 +!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 +B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 +B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 +B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 +!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 +B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 +!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 +!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 +B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 +B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 +B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 +!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 +B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 +B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 +!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 +B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 +B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 +!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 +!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 +B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 +B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 +!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 +B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 +B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 +B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 +B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 +!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 +!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 +!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 +B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 +B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 +B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 +!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 +B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 +!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 +B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 +B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 +B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 +!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 +!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 +B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 +!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 +B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 +B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 +B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 +!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 +B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 +B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 +B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 +B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 +!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 +!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 +!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 +B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 +B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 +B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 +B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 +B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 +!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 +B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 +!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 +B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 +B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 +B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 +B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 +!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 +B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 +B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 +!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 +B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 +B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 +B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 +!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 +!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 +!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 +B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 +B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 +B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 +!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 +B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 +!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 +!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 +B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 +B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 +B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 +!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 +!B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 +B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 +!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 +B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 +B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 +B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 +!B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 +!B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 +B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 +B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 +!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 +B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 +B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 +!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 +B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 +B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 +B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 +!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 +B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 +B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 +!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 +B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 +!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 +B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 +B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 +B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 +B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 +!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 +B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 +B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 +!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 +!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 +B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 +B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 +B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 +!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 +!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 +B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 +!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 +B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 +B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 +!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 +!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 +B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 +!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 +B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 +""" +pinloc_txt = """ +10 0 11 0 +101 13 13 0 +1 0 14 1 +102 13 13 1 +104 13 14 0 +105 13 14 1 +106 13 15 0 +107 13 15 1 +11 0 10 1 +112 12 17 1 +113 12 17 0 +114 11 17 1 +115 11 17 0 +116 10 17 1 +117 10 17 0 +118 9 17 1 +119 9 17 0 +12 0 10 0 +120 8 17 1 +121 8 17 0 +122 7 17 1 +128 7 17 0 +129 6 17 1 +134 5 17 1 +135 5 17 0 +136 4 17 1 +137 4 17 0 +138 3 17 1 +139 3 17 0 +141 2 17 1 +142 2 17 0 +143 1 17 1 +144 1 17 0 +19 0 9 1 +20 0 9 0 +2 0 14 0 +21 0 8 1 +22 0 8 0 +23 0 6 1 +24 0 6 0 +25 0 5 1 +26 0 5 0 +28 0 4 1 +29 0 4 0 +3 0 13 1 +31 0 3 1 +32 0 3 0 +33 0 2 1 +34 0 2 0 +37 1 0 0 +38 1 0 1 +39 2 0 0 +4 0 13 0 +41 2 0 1 +42 3 0 0 +43 3 0 1 +44 4 0 0 +45 4 0 1 +47 5 0 0 +48 5 0 1 +49 6 0 1 +50 7 0 0 +52 6 0 0 +56 7 0 1 +58 8 0 0 +60 8 0 1 +61 9 0 0 +62 9 0 1 +63 10 0 0 +64 10 0 1 +67 11 0 0 +68 11 0 1 +70 12 0 0 +7 0 12 1 +71 12 0 1 +73 13 1 0 +74 13 1 1 +75 13 2 0 +76 13 2 1 +78 13 3 1 +79 13 4 0 +8 0 12 0 +80 13 4 1 +81 13 6 0 +87 13 6 1 +88 13 7 0 +9 0 11 1 +90 13 7 1 +91 13 8 0 +93 13 8 1 +94 13 9 0 +95 13 9 1 +96 13 11 0 +97 13 11 1 +98 13 12 0 +99 13 12 1 +""" |