testsuite/synth/sns01/sns02.vhdl


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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;

entity sns02 is
  port (a : std_logic_vector(7 downto 0);
        b : out std_logic);
end sns02;

architecture behav of sns02 is
begin
  b <= or_reduce(a);
end behav;