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author | Tristan Gingold <tgingold@free.fr> | 2020-03-28 18:33:17 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-28 18:33:17 +0100 |
commit | 79267f4dc60753aac17f2192a9f6eee5e2ef7b75 (patch) | |
tree | 42b85051432b0a715fd00e240b124827b910d8f6 /testsuite/synth/sns01/sns02.vhdl | |
parent | 42ad5a45c7cc7e21ea5bfecffde045bef39597e6 (diff) | |
download | ghdl-79267f4dc60753aac17f2192a9f6eee5e2ef7b75.tar.gz ghdl-79267f4dc60753aac17f2192a9f6eee5e2ef7b75.tar.bz2 ghdl-79267f4dc60753aac17f2192a9f6eee5e2ef7b75.zip |
testsuite/synth: add testcase for previous commit.
Diffstat (limited to 'testsuite/synth/sns01/sns02.vhdl')
-rw-r--r-- | testsuite/synth/sns01/sns02.vhdl | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/testsuite/synth/sns01/sns02.vhdl b/testsuite/synth/sns01/sns02.vhdl new file mode 100644 index 000000000..c68ddbd90 --- /dev/null +++ b/testsuite/synth/sns01/sns02.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_misc.all; + +entity sns02 is + port (a : std_logic_vector(7 downto 0); + b : out std_logic); +end sns02; + +architecture behav of sns02 is +begin + b <= or_reduce(a); +end behav; |