testsuite/gna/issue2155/e.vhdl


1
2
3
4
5
6
7
8
9
10
11
12

library ieee;
use ieee.std_logic_1164.all;

use work.closely_related_arrays.all;

entity e is
end;

architecture behav of e is
begin
  assert sv (1) = std_logic_vector (uv (1)) severity failure;
end behav;