testsuite/gna/issue1672/repro.vhdl


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entity repro_sub is
  generic (num_ports : integer);
  port (clocks : bit_vector(0 to num_ports - 1));
end entity;

architecture a of repro_sub is
begin
end architecture;


entity repro is
end entity;

architecture a of repro is
  signal clock : bit := '0';
begin
  repro_sub_inst : entity work.repro_sub
    generic map (num_ports => 4)
    port map (clocks => (others => clock));
end architecture;