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-rw-r--r--testsuite/gna/issue1672/repro.vhdl20
1 files changed, 20 insertions, 0 deletions
diff --git a/testsuite/gna/issue1672/repro.vhdl b/testsuite/gna/issue1672/repro.vhdl
new file mode 100644
index 000000000..ad4ee55ea
--- /dev/null
+++ b/testsuite/gna/issue1672/repro.vhdl
@@ -0,0 +1,20 @@
+entity repro_sub is
+ generic (num_ports : integer);
+ port (clocks : bit_vector(0 to num_ports - 1));
+end entity;
+
+architecture a of repro_sub is
+begin
+end architecture;
+
+
+entity repro is
+end entity;
+
+architecture a of repro is
+ signal clock : bit := '0';
+begin
+ repro_sub_inst : entity work.repro_sub
+ generic map (num_ports => 4)
+ port map (clocks => (others => clock));
+end architecture;