testsuite/gna/issue1672/dut.vhdl


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library ieee;
use ieee.std_logic_1164.all;

entity dut is
  generic (
    num_ports : integer
  );
  port (
    clocks : std_logic_vector(0 to num_ports - 1)
  );
end entity;

architecture a of dut is

begin

end architecture;