testsuite/gna/bug0131/foo.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity foo is
end entity;

architecture fum of foo is
    signal counter:         unsigned (6 downto 0) := (others => '0');
begin
    process (counter) is
        constant DIV_FACTOR_FM_C:   unsigned (6 downto 0) := (others => '1');
        CONSTANT A : unsigned(6 DOWNTO 0) := "0010100";  -- 20
        CONSTANT B : unsigned(6 DOWNTO 0) := DIV_FACTOR_FM_C - 1;
    begin
        CASE counter IS
           WHEN A =>
           WHEN B =>
           WHEN OTHERS =>
         END CASE;
     end process;
end architecture;