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-rw-r--r--testsuite/gna/bug0131/foo.vhdl22
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diff --git a/testsuite/gna/bug0131/foo.vhdl b/testsuite/gna/bug0131/foo.vhdl
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+++ b/testsuite/gna/bug0131/foo.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity foo is
+end entity;
+
+architecture fum of foo is
+ signal counter: unsigned (6 downto 0) := (others => '0');
+begin
+ process (counter) is
+ constant DIV_FACTOR_FM_C: unsigned (6 downto 0) := (others => '1');
+ CONSTANT A : unsigned(6 DOWNTO 0) := "0010100"; -- 20
+ CONSTANT B : unsigned(6 DOWNTO 0) := DIV_FACTOR_FM_C - 1;
+ begin
+ CASE counter IS
+ WHEN A =>
+ WHEN B =>
+ WHEN OTHERS =>
+ END CASE;
+ end process;
+end architecture;