| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | testsuite/synth: add tests for memory ports order. | Tristan Gingold | 2020-02-23 | 1 | -1/+2 |
| * | testsuite/synth: add a source for mem01 | Tristan Gingold | 2020-02-20 | 1 | -0/+2 |
| * | testsuite/synth: merge ram01 to mem01, add NOTES.txt | Tristan Gingold | 2020-02-18 | 1 | -0/+9 |
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index : iCE40/ghdl | |
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