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| author | Tristan Gingold <tgingold@free.fr> | 2020-02-20 07:41:18 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-02-20 07:48:44 +0100 |
| commit | cf9d17b816445b414bf1855bff8bd070ea4da1b6 (patch) | |
| tree | d475dad8e313ec9c075bf051b1325ce1d4de48e8 /testsuite/synth/mem01/NOTES.txt | |
| parent | edfe8e0915a640537617d0afb3876ce2603bda81 (diff) | |
| download | ghdl-cf9d17b816445b414bf1855bff8bd070ea4da1b6.tar.gz ghdl-cf9d17b816445b414bf1855bff8bd070ea4da1b6.tar.bz2 ghdl-cf9d17b816445b414bf1855bff8bd070ea4da1b6.zip | |
testsuite/synth: add a source for mem01
Diffstat (limited to 'testsuite/synth/mem01/NOTES.txt')
| -rw-r--r-- | testsuite/synth/mem01/NOTES.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/testsuite/synth/mem01/NOTES.txt b/testsuite/synth/mem01/NOTES.txt index 84edd5041..3c362c073 100644 --- a/testsuite/synth/mem01/NOTES.txt +++ b/testsuite/synth/mem01/NOTES.txt @@ -3,7 +3,9 @@ Tests for RAMs rom1: asynchronous ROM srom01: Read (initialized ROM). + sram01: Read+Write (at the same address). +sram02: Write+Read (at the same address). dpram1: Read+Write (using signals, without enables) dpram2: Read+Write (using a variable, without enables) dpram3: Read+Write (like dpram2 but downto) |