iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth: cap max in synth_slice_suffix	Tristan Gingold	2019-11-03	1	-1/+8
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*	netlists-expands: rewrite generate_muxes.	Tristan Gingold	2019-11-03	1	-24/+102
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*	netlists-expands: use a safe walk.	Tristan Gingold	2019-11-03	1	-1/+3
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*	synth: add support for inout variable interfaces.	Tristan Gingold	2019-11-01	2	-3/+4
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*	synth-values: handle value_const for is_equal.	Tristan Gingold	2019-11-01	1	-0/+5
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*	synth: handle nested if generate statements.	Tristan Gingold	2019-11-01	2	-21/+29
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*	netlits: fix memidx order.	Tristan Gingold	2019-11-01	2	-39/+52
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*	netlists-dump: improve output.	Tristan Gingold	2019-11-01	1	-10/+11
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*	netlists-expands: expand dyn_insert	Tristan Gingold	2019-11-01	2	-42/+174
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*	psl-nfa-utils: move active state in merge_state.	Tristan Gingold	2019-10-31	1	-0/+5
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*	vhdl-prints: handle more constructs in psl vunit.	Tristan Gingold	2019-10-31	1	-0/+5
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*	ghdlsynth_gates.h: regenerate.	Tristan Gingold	2019-10-31	1	-0/+4
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*	synth: handle attributes in vunit.	Tristan Gingold	2019-10-30	1	-1/+86
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*	netlists: add formal input gates.	Tristan Gingold	2019-10-30	3	-0/+44
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*	vhdl: allow attributes in vunit declarations.	Tristan Gingold	2019-10-30	6	-200/+216
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*	Add names for formal input gates/attributes.	Tristan Gingold	2019-10-30	2	-1/+13
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*	netlists-expands: handle 2d arrays.	Tristan Gingold	2019-10-28	1	-83/+72
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*	synth: adjust computation of max for dyn_extract.	Tristan Gingold	2019-10-28	3	-8/+10
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*	netlists-disp_vhdl: prefix of strunc/utrunc cannot be a constant.	Tristan Gingold	2019-10-28	1	-1/+3
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*	synth-expr (synth_slice_suffix): compute max value for slices.	Tristan Gingold	2019-10-27	1	-1/+4
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*	netlists-expand: truncate address if needed.	Tristan Gingold	2019-10-27	1	-0/+10
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*	ghdlsynth: add -de option.	Tristan Gingold	2019-10-27	1	-0/+3
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*	netlists: add code to expand dyn_extract gates (WIP).	Tristan Gingold	2019-10-27	5	-1/+259
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*	netlists: change Loc parameter of synth_case.	Tristan Gingold	2019-10-27	5	-6/+21
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*	synth: create build2_concat from netlists-concat.	Tristan Gingold	2019-10-27	7	-38/+48
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*	netlists-butils: extract synth_case from synth.stmts.	Tristan Gingold	2019-10-26	3	-149/+206
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*	synth: handle concurrent signal assignment in vunits.	Tristan Gingold	2019-10-25	2	-83/+91
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*	vhdl-canon: handle simple signal assignment in vunits.	Tristan Gingold	2019-10-25	1	-273/+272
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*	vhdl-canon: extract canon_concurrent_label.	Tristan Gingold	2019-10-25	1	-20/+25
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*	vhdl-annotations: extract annotate_concurrent_statement.	Tristan Gingold	2019-10-25	1	-47/+53
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*	vhdl-annotations: minor renaming.	Tristan Gingold	2019-10-25	1	-8/+8
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*	vhdl: extract sem_concurrent_statement, to handle hdl stmt in vunits.	Tristan Gingold	2019-10-25	4	-119/+122
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*	vhdl-parse_psl: add comments.	Tristan Gingold	2019-10-25	1	-8/+71
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*	vhdl-parse: do not scan PSL keywords in vunit declarations.	Tristan Gingold	2019-10-24	1	-0/+4
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*	vhdl/translate: elaborate dependencies of configurations. Fix #984	Tristan Gingold	2019-10-24	1	-0/+4
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*	synth: add support for declarations in vunits.	Tristan Gingold	2019-10-23	2	-4/+27
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*	vhdl-prints: do not crash on vunit declarations.	Tristan Gingold	2019-10-23	1	-0/+4
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*	vhdl-annotations: handle some declarations in vunits.	Tristan Gingold	2019-10-23	1	-0/+6
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*	vhdl-canon: handle some declarations in vunits.	Tristan Gingold	2019-10-23	1	-2/+18
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*	vhdl-sem_psl: analyze some declarations.	Tristan Gingold	2019-10-23	1	-0/+18
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*	vhdl-sem_decls: make sem_declaration public.	Tristan Gingold	2019-10-23	5	-14/+31
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*	vhdl-sem_decls: extract sem_declaration.	Tristan Gingold	2019-10-23	1	-121/+118
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*	netlists-dump: dump input net width.	Tristan Gingold	2019-10-23	1	-0/+2
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*	vhdl-sem_decls: add comment.	Tristan Gingold	2019-10-21	1	-0/+3
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*	vhdl-parse: parse declarations in vunit.	Tristan Gingold	2019-10-21	1	-327/+352
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*	Regenerate ghdlsynth_gates.h	Tristan Gingold	2019-10-21	1	-0/+1
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*	vhdl: handle labels in verification units.	Tristan Gingold	2019-10-21	1	-8/+62
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*	synth: generate cover for assertion precedent.	Tristan Gingold	2019-10-21	5	-84/+103
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*	psl: add active state.	Tristan Gingold	2019-10-21	5	-20/+78
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*	vhdl-prints: handle restrict in vunit.	Tristan Gingold	2019-10-21	1	-0/+2
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