iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: add id_inout gate to handle inout behaviour. Fir #1166	Tristan Gingold	2020-03-23	5	-13/+79
*	synth-disp_vhdl: do not wrap inout ports. For #1166	Tristan Gingold	2020-03-22	8	-17/+51
*	vhdl-scanner: handle pragma translate on/off.	Tristan Gingold	2020-03-22	1	-13/+26
*	synth: do not crash immediately on access type.	Tristan Gingold	2020-03-22	3	-34/+70
*	synth: handle ieee.numeric_std.to_01	Tristan Gingold	2020-03-22	5	-23/+55
*	synth: handle reuse of inferred dff in the same process.	Tristan Gingold	2020-03-22	3	-35/+98
*	netlists: add id_nop gate.	Tristan Gingold	2020-03-22	6	-11/+36
*	synth-environment: keep order of seq_assign in phi nodes.	Tristan Gingold	2020-03-21	2	-5/+12
*	synth: handle numeric_std minimum/maximum. Fix #1168	Tristan Gingold	2020-03-21	5	-261/+296
*	vhdl: recognize minimum/maximum in numeric_std. For #1168	Tristan Gingold	2020-03-21	2	-0/+54
*	synth-static_oper: handle not for signed and unsigned. Fix #1167	Tristan Gingold	2020-03-21	1	-1/+3
*	vhdl-sem_assocs: remove duplicate error message for non-existing interface.	Tristan Gingold	2020-03-21	1	-8/+0
*	synth-stmts: avoid crash for index in record. Fix #1163	Tristan Gingold	2020-03-20	1	-8/+2
*	synth-expr: fix handling of value_const in synth_subtype_conversion. Fix #1165	Tristan Gingold	2020-03-19	1	-1/+2
*	synth-insts: also handle indexed name for synth_type_of_object. Fix #1164	Tristan Gingold	2020-03-19	1	-0/+8
*	netlists-builders: allow null net for all dffs. Fix #1162	Tristan Gingold	2020-03-19	1	-2/+0
*	vhdl-sem_expr: fix a wrong check in choices. For #1161	Tristan Gingold	2020-03-19	1	-0/+5
*	synth-expr: handle vectors in aggregates. For #1161	Tristan Gingold	2020-03-19	1	-9/+28
*	synth-expr: handle length attribute for subtypes. Fix #1160	Tristan Gingold	2020-03-18	1	-5/+13
*	synth: refactoring inference (WIP).	Tristan Gingold	2020-03-15	2	-55/+87
*	trans-chap7: minor renaming.	Tristan Gingold	2020-03-14	1	-5/+5
*	synth: handle more operations from synsopsys packages.	Tristan Gingold	2020-03-14	3	-31/+63
*	synth: handle more operators from std_logic_arith.	Tristan Gingold	2020-03-14	1	-4/+13
*	synth-static_oper: handle minimum/maximum for integers. Fix #1158	Tristan Gingold	2020-03-14	1	-2/+4
*	synth: propagate more errors.	Tristan Gingold	2020-03-14	2	-0/+8
*	vhdl-ieee-std_logic_arith: fix warnings.	Tristan Gingold	2020-03-14	1	-12/+5
*	std_names: add *_reduce names.	Tristan Gingold	2020-03-13	2	-5/+17
*	vhdl: recognize more std_logic_arith operations.	Tristan Gingold	2020-03-13	2	-2/+175
*	synth: handle static sub uns/nat.	Tristan Gingold	2020-03-13	3	-0/+51
*	psl-rewrites: handle N_Paren_Prop (simply discard).	Tristan Gingold	2020-03-13	1	-0/+3
*	synth: handle div/rem/mod operations. Fix #1157	Tristan Gingold	2020-03-13	2	-60/+79
*	synth-stmts: strip const in if statement.	Tristan Gingold	2020-03-13	1	-0/+1
*	synth-static_oper: handle unsigned "<".	Tristan Gingold	2020-03-13	2	-1/+66
*	synth-insts: handle record in generics.	Tristan Gingold	2020-03-13	2	-23/+57
*	synth-static_oper: handle static net for add_uns_nat.	Tristan Gingold	2020-03-13	1	-5/+14
*	netlists: handle more case of 0 sized nets.	Tristan Gingold	2020-03-13	3	-3/+5
*	synth-insts: handle output individual assoc for components.	Tristan Gingold	2020-03-13	1	-18/+3
*	synth-insts: handle input individual associations for components.	Tristan Gingold	2020-03-13	1	-55/+49
*	synth: propagate more errors.	Tristan Gingold	2020-03-13	3	-1/+11
*	vhdl-scanner: abstract Scan_Comment_Pragma	Tristan Gingold	2020-03-13	1	-32/+40
*	synth-expr: handle reverse_range attribute.	Tristan Gingold	2020-03-13	1	-0/+22
*	synth: handle conversions for enumerations.	Tristan Gingold	2020-03-13	1	-1/+6
*	psl: keep denoting names in the PSL ast.	Tristan Gingold	2020-03-13	19	-40/+129
*	vhdl-sem_lib: also disable warnings when parsing	Tristan Gingold	2020-03-11	1	-10/+17
*	synth-expr: propagate error.	Tristan Gingold	2020-03-11	1	-0/+3
*	synth: implement more conversions.	Tristan Gingold	2020-03-11	4	-41/+50
*	vhdl-ieee-std_logic_arith: recognize more conversions.	Tristan Gingold	2020-03-11	4	-6/+21
*	synth: improve error message.	Tristan Gingold	2020-03-11	2	-2/+2
*	vhdl-ieee-std_logic_unsigned: recognize more operations.	Tristan Gingold	2020-03-11	2	-0/+17
*	synth: improve error handling.	Tristan Gingold	2020-03-11	4	-26/+81