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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-11 18:42:01 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-11 18:42:01 +0100 |
| commit | cae204093418e82299b93af809007aadd4cde36d (patch) | |
| tree | 7370a644f30f66ce7a94df0b49c4ede8d9e1f578 /src | |
| parent | 4c9651dfbb4aeb4bd22b1b6eb5436119f599f8e4 (diff) | |
| download | ghdl-cae204093418e82299b93af809007aadd4cde36d.tar.gz ghdl-cae204093418e82299b93af809007aadd4cde36d.tar.bz2 ghdl-cae204093418e82299b93af809007aadd4cde36d.zip | |
vhdl-ieee-std_logic_arith: recognize more conversions.
Diffstat (limited to 'src')
| -rw-r--r-- | src/std_names.adb | 1 | ||||
| -rw-r--r-- | src/std_names.ads | 11 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_arith.adb | 8 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 7 |
4 files changed, 21 insertions, 6 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index 1a7de9a6a..2511c779c 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -655,6 +655,7 @@ package body Std_Names is Def ("conv_signed", Name_Conv_Signed); Def ("conv_unsigned", Name_Conv_Unsigned); Def ("conv_integer", Name_Conv_Integer); + Def ("conv_std_logic_vector", Name_Conv_Std_Logic_Vector); Def ("ceil", Name_Ceil); Def ("round", Name_Round); Def ("log2", Name_Log2); diff --git a/src/std_names.ads b/src/std_names.ads index d6c7621c6..5b54d14e4 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -738,11 +738,12 @@ package Std_Names is Name_Conv_Signed : constant Name_Id := Name_First_Ieee_Name + 025; Name_Conv_Unsigned : constant Name_Id := Name_First_Ieee_Name + 026; Name_Conv_Integer : constant Name_Id := Name_First_Ieee_Name + 027; - Name_Ceil : constant Name_Id := Name_First_Ieee_Name + 028; - Name_Round : constant Name_Id := Name_First_Ieee_Name + 029; - Name_Log2 : constant Name_Id := Name_First_Ieee_Name + 030; - Name_Sin : constant Name_Id := Name_First_Ieee_Name + 031; - Name_Cos : constant Name_Id := Name_First_Ieee_Name + 032; + Name_Conv_Std_Logic_Vector : constant Name_Id := Name_First_Ieee_Name + 028; + Name_Ceil : constant Name_Id := Name_First_Ieee_Name + 029; + Name_Round : constant Name_Id := Name_First_Ieee_Name + 030; + Name_Log2 : constant Name_Id := Name_First_Ieee_Name + 031; + Name_Sin : constant Name_Id := Name_First_Ieee_Name + 032; + Name_Cos : constant Name_Id := Name_First_Ieee_Name + 033; Name_Last_Ieee_Name : constant Name_Id := Name_Cos; Name_First_Synthesis : constant Name_Id := Name_Last_Ieee_Name + 1; diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb index 28bf913a1..e8a7fbd1b 100644 --- a/src/vhdl/vhdl-ieee-std_logic_arith.adb +++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb @@ -45,6 +45,12 @@ package body Vhdl.Ieee.Std_Logic_Arith is Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Int, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Log); + Conv_Vec_Patterns : constant Conv_Pattern_Type := + (Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Log); + Error : exception; procedure Extract_Declarations (Pkg : Iir_Package_Declaration) @@ -152,6 +158,8 @@ package body Vhdl.Ieee.Std_Logic_Arith is case Get_Identifier (Decl) is when Name_Conv_Unsigned => Def := Handle_Conv (Conv_Uns_Patterns); + when Name_Conv_Std_Logic_Vector => + Def := Handle_Conv (Conv_Vec_Patterns); when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 54fba3db2..ed83cd157 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5746,7 +5746,12 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Int, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Sgn, - Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Log + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Log, + + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Log ); -- Return TRUE iff FUNC is a short-cut predefined function. |