aboutsummaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* trans-chap8: adjust conditions to pass parameters. Fix #2104Tristan Gingold2022-06-221-2/+9
|
* vhdl-sem.adb: avoid a crash on conformance error. Fix #2103Tristan Gingold2022-06-211-2/+2
|
* vhdl-sem_lib: do not disable warnings for files in -c/-rTristan Gingold2022-06-191-1/+5
|
* trans-chap7: translate anonymous subtype of overflow literal. Fox #2066Tristan Gingold2022-06-191-2/+6
|
* vhdl-sem_expr: check expression index range for aggregate. Fix #2066Tristan Gingold2022-06-191-0/+25
|
* synth-vhdl_insts(synth_single_input_assoc): handle type conversion.Tristan Gingold2022-06-162-4/+13
| | | | Fix #2099
* vhdl-sem.adb(are_trees_equal): handle simple aggregate.Tristan Gingold2022-06-161-14/+12
| | | | Fix #2098
* vhdl/translate: handle inertial association in recursive instantiationTristan Gingold2022-06-162-2/+16
| | | | Fix #2065
* vhdl-sem_names: handle element and subtype attributes for type conv.Tristan Gingold2022-06-161-22/+26
| | | | Fix #2097
* vhdl-sem_expr: do not attribute element or subtype attributes as expr.Tristan Gingold2022-06-161-0/+2
| | | | For #2097
* vhdl: handle 'element in 'range. Fix #2071Tristan Gingold2022-06-152-23/+104
|
* Add commentsTristan Gingold2022-06-152-1/+2
|
* netlists-rename: handle handle signal instances. Fix #2093Tristan Gingold2022-06-153-2/+28
|
* src/synth: add netlists.rename to rename identifiers. Fix #2054Tristan Gingold2022-06-144-2/+132
|
* netlists-disp_verilog: do not display blackboxes. Fix #2092Tristan Gingold2022-06-131-0/+5
|
* netlists-disp_verilog: Use blocking assignments in non-clocked blocksAnton Blanchard2022-06-131-10/+10
|
* vhdl: add a parent field to protected_type_declaration. Fix #2091Tristan Gingold2022-06-123-265/+271
|
* synth-vhdl_insts: handle actual conversion function. Fix #2090Tristan Gingold2022-06-121-12/+38
|
* elab-vhdl_insts: eval inertial expressions to get the type. Fix #2089Tristan Gingold2022-06-122-7/+18
|
* vhdl-nodes: add Inertial_Flag for association_element_by_expressionTristan Gingold2022-06-125-302/+347
|
* elab-vhdl_types(Synth_Array_Attribute): handle dimension parameterTristan Gingold2022-06-111-1/+3
| | | | Fix #2088
* synth-environment(Merge_Dyn_Insert): disable transformation.Tristan Gingold2022-06-111-1/+3
| | | | | | Do not transform a Dyn_Insert into a Dyn_Insert_En, to avoid spurious latch detection. For #2086
* netlists-memories: handle negation for In_Conjunction. Fix #2086Tristan Gingold2022-06-111-8/+3
|
* synth-vhdl_eval: add support for more operationsTristan Gingold2022-06-111-1/+10
|
* vhdl: recognize ieee.math_real.sign, fix is_x recogn.Tristan Gingold2022-06-117-18/+51
|
* deleted pragma messagesGuiltybyte2022-06-091-2/+0
|
* Only enable backtrace on linux if glibc is presentGuiltybyte2022-06-091-1/+3
|
* elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtypeTristan Gingold2022-06-097-30/+64
| | | | Fix #2085
* vhdl-annotations: avoid a crash with subtype attribute in array.Tristan Gingold2022-06-093-5/+16
| | | | Fix #2084
* synth-vhdl_expr.adb: use base type for indexed names. Fix #2083Tristan Gingold2022-06-081-1/+2
|
* synth-vhdl_expr: add an hook for signal attributesTristan Gingold2022-06-082-0/+11
|
* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-071-8/+17
|
* vhdl-sem: adjust condition to set suspend_state on proceduresTristan Gingold2022-06-073-15/+36
|
* elab-vhdl_context: also handle generic subprogramsTristan Gingold2022-06-071-2/+6
|
* options.adb: add commandsTristan Gingold2022-06-071-2/+2
|
* errorout: add nowrite warning. Fix #2081Tristan Gingold2022-06-075-8/+16
| | | | During synthesis, emit a specific warning if a net is not assigned
* vhdl-parse.adb: fix uninitialized variable, for #2076Tristan Gingold2022-06-061-0/+1
|
* vhdl-sem_names: avoid a crash on incorrect selected name. For #2076Tristan Gingold2022-06-061-1/+2
|
* vhdl-parse: avoid a crash with return identifier. Fox #2076Tristan Gingold2022-06-061-1/+7
|
* synth-vhdl_stmts: fix handling of instantiated subprogramsTristan Gingold2022-06-061-1/+3
|
* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-061-1/+16
|
* synth-vhdl_stmts: handle alias in assignment expressionTristan Gingold2022-06-063-2/+24
|
* vhdl-ieee-math_real: recognize more operationsTristan Gingold2022-06-062-12/+45
|
* synth-vhdl_eval: recognize and handle to_stdulogicvectorTristan Gingold2022-06-063-2/+17
|
* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-052-37/+112
|
* vhdl: recognize more predefined ieee functions and operatorsTristan Gingold2022-06-054-7/+112
|
* synth-vhdl_eval: handle more operations (sgn/uns reduce)Tristan Gingold2022-06-051-6/+16
|
* synth-vhdl-eval: handle more operationsTristan Gingold2022-06-054-31/+272
|
* vhdl-ieee-numeric: recognize vector/scalar operationsTristan Gingold2022-06-052-3/+51
|
* synth-vhdl_oper: handle more bit_vector operations. Fix #2074Tristan Gingold2022-06-051-8/+13
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-21 13:53:04 +0000