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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-11 06:21:48 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-11 15:02:48 +0200 |
| commit | 61fcaafdd2005cde56c7336002bbab860af0f677 (patch) | |
| tree | 3779398a2aa33873dfd461bb51eb0c9606387fa9 /src | |
| parent | bb357cf03c7e956db1539712fd64353b6d87872d (diff) | |
| download | ghdl-61fcaafdd2005cde56c7336002bbab860af0f677.tar.gz ghdl-61fcaafdd2005cde56c7336002bbab860af0f677.tar.bz2 ghdl-61fcaafdd2005cde56c7336002bbab860af0f677.zip | |
synth-vhdl_eval: add support for more operations
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_eval.adb | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index 96564be6a..ab1304190 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -2218,6 +2218,14 @@ package body Synth.Vhdl_Eval is B := To_X01 (B); return Create_Memory_U8 (Std_Ulogic'Pos (B), Res_Typ); end; + when Iir_Predefined_Ieee_1164_To_X01Z_Log => + declare + B : Std_Ulogic; + begin + B := Read_Std_Logic (Param1.Val.Mem, 0); + B := Map_X01Z (B); + return Create_Memory_U8 (Std_Ulogic'Pos (B), Res_Typ); + end; when Iir_Predefined_Ieee_1164_To_X01_Slv | Iir_Predefined_Ieee_Numeric_Std_To_X01_Uns | Iir_Predefined_Ieee_Numeric_Std_To_X01_Sgn => @@ -2292,7 +2300,8 @@ package body Synth.Vhdl_Eval is return Res; end; - when Iir_Predefined_Ieee_1164_To_01_Slv_Log => + when Iir_Predefined_Ieee_1164_To_01_Slv_Log + | Iir_Predefined_Ieee_Numeric_Std_To_01_Uns => declare Len : constant Uns32 := Param1.Typ.Abound.Len; S : Std_Ulogic; |