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* vhdl-sem_names: finish prefix of element attribute namesTristan Gingold2023-01-121-22/+32
* synth: report values in bound errorsTristan Gingold2023-01-122-9/+40
* synth: use same wording for direction mismatch as simulationTristan Gingold2023-01-121-1/+2
* synth-vhdl_eval: handle to_X01 for bit to std_ulogic.Tristan Gingold2023-01-113-0/+39
* synth: handle entity attributesTristan Gingold2023-01-111-2/+18
* synth: handle universal r*i and i*r mul, physical mod.Tristan Gingold2023-01-111-1/+9
* synth: handle element attributeTristan Gingold2023-01-114-9/+39
* synth: fix matching comparaison tablesTristan Gingold2023-01-111-27/+27
* synth: rework error handling in file operationsTristan Gingold2023-01-113-43/+63
* simul: avoid a crash after an error in a conditionTristan Gingold2023-01-111-1/+6
* synth: improve support of PSL endpointsTristan Gingold2023-01-114-4/+8
* synth: avoid a crash on very large object typesTristan Gingold2023-01-111-0/+3
* synth: check float ranges in subtype conversionTristan Gingold2023-01-113-2/+25
* simul: allow function calls in signal association by valueTristan Gingold2023-01-111-0/+2
* synth: add a check for v87 concatenationsTristan Gingold2023-01-111-1/+6
* synth: support constant declarations in protected typesTristan Gingold2023-01-111-0/+1
* vhdl-configuration: relax top-level unit restrictionsTristan Gingold2023-01-111-4/+5
* synth: handle file subtypeTristan Gingold2023-01-112-1/+9
* simul: improve support of psl in debuggerTristan Gingold2023-01-112-4/+13
* simul: handle psl assume directivesTristan Gingold2023-01-111-0/+2
* simul: add sensitivity for psl processesTristan Gingold2023-01-111-4/+7
* synth: allow file declaration in protected objectsTristan Gingold2023-01-111-1/+2
* elab-vhdl_files: remove incorrect assertionTristan Gingold2023-01-111-1/+0
* simul: improve assertion messages for pslTristan Gingold2023-01-112-28/+45
* synth: avoid a crash after error on signal associationTristan Gingold2023-01-111-2/+6
* simul: add debug command 'run -s'Tristan Gingold2023-01-113-8/+18
* simul: handle array element resolutionTristan Gingold2023-01-111-1/+6
* synth: also elaborate dependencies of configurationsTristan Gingold2023-01-111-0/+4
* simul: improve debugger outputTristan Gingold2023-01-111-5/+5
* simul: handle -gGEN=VAL options after the unitTristan Gingold2023-01-111-7/+41
* synth: fix memory allocation in predefined function callsTristan Gingold2023-01-103-1/+8
* synth: adjust unshare_type for unbounded composite typesTristan Gingold2023-01-101-4/+14
* synth: check rem/mod by 0Tristan Gingold2023-01-101-2/+14
* simul: enable all debug features during elaborationTristan Gingold2023-01-102-5/+3
* synth: handle indexes in arrays conversionTristan Gingold2023-01-105-17/+85
* vhdl-sem_inst: adjust instantiation of interface typeTristan Gingold2023-01-101-0/+3
* synth: add comments, minor rewriteTristan Gingold2023-01-103-6/+10
* vhdl-sem_inst: fix build of suspend state chainTristan Gingold2023-01-101-1/+1
* vhdl-prints: handle suspend state declarations and statementsTristan Gingold2023-01-101-2/+22
* synth: also fix #2299Tristan Gingold2023-01-101-3/+6
* simul: handle inertial assignmentsTristan Gingold2023-01-101-2/+14
* synth-vhdl_aggr: optimize common aggregateTristan Gingold2023-01-102-17/+38
* Dot output ports (#2305)cderrien2023-01-101-53/+127
* synth: always create shared variablesTristan Gingold2023-01-093-34/+22
* synth: improve support of individual association for subprogramsTristan Gingold2023-01-091-1/+2
* synth-vhdl_aggr: improve support of very large aggregatesTristan Gingold2023-01-091-1/+2
* synth: improve support of subtype attributeTristan Gingold2023-01-091-4/+4
* simul: set assertion hook before elaborationTristan Gingold2023-01-091-3/+3
* elab-vhdl_expr(exec_name_subtype): handle image attributeTristan Gingold2023-01-091-0/+8
* simul-vhdl_simul: fix effective value writesTristan Gingold2023-01-091-1/+20
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