| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
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| * | synth: add support for memories. | Tristan Gingold | 2019-07-29 | 15 | -152/+445 | |
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| * | synth: remove extract_bound (trivial). | Tristan Gingold | 2019-07-28 | 5 | -15/+6 | |
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| * | synth: unconstrained arrays. | Tristan Gingold | 2019-07-28 | 5 | -17/+71 | |
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| * | synth: preliminary support of dynamic indexing. | Tristan Gingold | 2019-07-28 | 13 | -740/+956 | |
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| * | vhdl: linearize analyze and evaluation of concat operators. | Tristan Gingold | 2019-07-26 | 5 | -360/+647 | |
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| * | synth: rework range. | Tristan Gingold | 2019-07-26 | 5 | -48/+52 | |
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| * | synth: preliminary support of integer subtypes. | Tristan Gingold | 2019-07-26 | 8 | -42/+68 | |
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| * | synth: handle array aggregate. | Tristan Gingold | 2019-07-26 | 2 | -27/+32 | |
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| * | synth: handle bit. | Tristan Gingold | 2019-07-25 | 3 | -4/+11 | |
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| * | synth: array inequality, integer in choices. | Tristan Gingold | 2019-07-25 | 2 | -0/+11 | |
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| * | vhdl+synth: recognize /= to std_logic_unsigned. | Tristan Gingold | 2019-07-25 | 3 | -1/+16 | |
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| * | vhdl: handle (discard) more pragmas. | Tristan Gingold | 2019-07-25 | 3 | -1/+19 | |
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| * | synth: save and display locations for instances. | Tristan Gingold | 2019-07-25 | 8 | -66/+247 | |
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| * | synth: fix incorrect slice in disp_vhdl for Insert. | Tristan Gingold | 2019-07-25 | 1 | -6/+1 | |
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| * | vhdl annotations: fix annotation of type in interface list. | Tristan Gingold | 2019-07-24 | 1 | -0/+1 | |
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| * | synth: fix bad ordering in case statement. | Tristan Gingold | 2019-07-24 | 1 | -2/+3 | |
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| * | synth: do not consider (unrecognized) ieee functions as user functions. | Tristan Gingold | 2019-07-24 | 1 | -0/+19 | |
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| * | synth: enable handling of pragma translate_on/off. | Tristan Gingold | 2019-07-24 | 1 | -0/+3 | |
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| * | vhdl scanner: handle pragma translate_on/translate_off. | Tristan Gingold | 2019-07-24 | 5 | -5/+109 | |
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| * | synth: handle resize. | Tristan Gingold | 2019-07-24 | 1 | -0/+15 | |
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| * | synth: handle record type declarations. | Tristan Gingold | 2019-07-24 | 1 | -1/+11 | |
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| * | vhdl: recognize resize function. | Tristan Gingold | 2019-07-24 | 4 | -3/+43 | |
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| * | synth: fix slice/indexed assignment that partially override previous assign. | Tristan Gingold | 2019-07-23 | 1 | -5/+8 | |
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| * | synth: add more operators. | Tristan Gingold | 2019-07-23 | 1 | -1/+34 | |
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| * | synth: fix to_unsigned. | Tristan Gingold | 2019-07-23 | 1 | -2/+2 | |
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| * | synth: use original entity to display netlist. | Tristan Gingold | 2019-07-23 | 7 | -22/+314 | |
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| * | vhdl-prints: improve output for ports/generics. | Tristan Gingold | 2019-07-22 | 1 | -5/+27 | |
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| * | synth: remove bounds (unused) for ports. | Tristan Gingold | 2019-07-22 | 4 | -13/+4 | |
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| * | ghdlsynth: preliminary work for wrapped generation. | Tristan Gingold | 2019-07-22 | 1 | -1/+8 | |
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| * | synth: minor refactoring in netlists.disp_vhdl | Tristan Gingold | 2019-07-22 | 2 | -47/+54 | |
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| * | synth: minor rework. | Tristan Gingold | 2019-07-22 | 3 | -10/+37 | |
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| * | synth: rework names. | Tristan Gingold | 2019-07-22 | 6 | -24/+25 | |
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| * | add port width utility function for yosys (#876) | Pepijn de Vos | 2019-07-21 | 4 | -0/+18 | |
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| * | synth: improve output (id_extract). | Tristan Gingold | 2019-07-20 | 1 | -6/+12 | |
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| * | synth: improve output (for id_insert). | Tristan Gingold | 2019-07-20 | 1 | -11/+18 | |
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| * | synth: add support for concurrent selected signal assignment. | Tristan Gingold | 2019-07-20 | 1 | -2/+138 | |
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| * | synth: support index of a constant. | Tristan Gingold | 2019-07-20 | 1 | -0/+4 | |
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| * | synth: initial support for for-generate statement. | Tristan Gingold | 2019-07-20 | 3 | -34/+97 | |
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| * | synth: add and merge phi within a function. | Tristan Gingold | 2019-07-20 | 1 | -0/+5 | |
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| * | synth: fix aggregate vectorize direction. | Tristan Gingold | 2019-07-20 | 2 | -5/+6 | |
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| * | synth: add concatn gate | Tristan Gingold | 2019-07-19 | 9 | -32/+126 | |
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| * | synth: finalize concurrent assignments (WIP). | Tristan Gingold | 2019-07-19 | 6 | -33/+342 | |
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| * | synth: add const_z gate. | Tristan Gingold | 2019-07-19 | 4 | -3/+33 | |
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| * | errorout: handle %v for values. | Tristan Gingold | 2019-07-19 | 2 | -1/+36 | |
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| * | synth: make more types private. | Tristan Gingold | 2019-07-17 | 2 | -35/+48 | |
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| * | synth: make type Wire_Id_Record private. | Tristan Gingold | 2019-07-17 | 7 | -44/+74 | |
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| * | synth: renaming of Assign to Seq_Assign. | Tristan Gingold | 2019-07-17 | 6 | -79/+82 | |
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| * | synth: add comments. | Tristan Gingold | 2019-07-17 | 2 | -0/+2 | |
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| * | vhdl: add a comment. | Tristan Gingold | 2019-07-16 | 1 | -0/+3 | |
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| * | synth: add > and >= operators (#870) | Pepijn de Vos | 2019-07-16 | 6 | -25/+118 | |
| | | | | | | | * synth: add > and >= operators * synth: update ghdlsynth_gates.h | |||||
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index : iCE40/ghdl | |
| clone of https://github.com/ghdl/ghdl |
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