iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	vhdl: fix unused warning on protected variable.	Tristan Gingold	2019-09-06	1	-0/+1
*	vhdl: handle P32 in connect_scalar. Fix #918	Tristan Gingold	2019-09-05	1	-1/+2
*	synth: handle const record aggregates.	Tristan Gingold	2019-09-05	4	-21/+64
*	synth: handle non-constant array aggregates.	Tristan Gingold	2019-09-05	2	-1/+15
*	synth: add netlists.concats	Tristan Gingold	2019-09-05	3	-31/+140
*	synth: add value_const_array.	Tristan Gingold	2019-09-05	4	-18/+68
*	synth-disp_vhdl: handle arrays in disp_out_converter.	Tristan Gingold	2019-09-05	1	-1/+19
*	synth: handle const_bit in disp_constant_inline.	Tristan Gingold	2019-09-04	1	-0/+4
*	synth: handle large width in get_net.	Tristan Gingold	2019-09-04	2	-4/+14
*	vhdl: do not crash on attribute with a type conversion prefix.	Tristan Gingold	2019-09-04	1	-2/+3
*	synth-disp_vhdl: handle records for outputs.	Tristan Gingold	2019-09-04	1	-42/+76
*	synth-disp_vhdl: handle record for input ports.	Tristan Gingold	2019-09-03	8	-44/+114
*	synth: subtype conversion before compare.	Tristan Gingold	2019-09-03	1	-2/+7
*	synth: handle conditional variable assignment.	Tristan Gingold	2019-09-02	1	-0/+34
*	vhdl: renames Conditional_Expression to Conditional_Expression_Chain.	Tristan Gingold	2019-09-02	8	-37/+40
*	vhdl synth: recognize more operators (add uns log).	Tristan Gingold	2019-09-02	3	-9/+62
*	synth: remove insert gate.	Tristan Gingold	2019-08-31	4	-70/+0
*	synth: improve synth_uresize.	Tristan Gingold	2019-08-31	3	-26/+50
*	synth: elab subprogram interfaces subtype	Tristan Gingold	2019-08-31	1	-2/+13
*	[PATCH] synth-environment: fix thinkos.	Tristan Gingold	2019-08-31	1	-14/+57
*	synth: add physical division (#904)	tgingold	2019-08-30	1	-1/+11
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\| *	synth: added division of physical type	Martin Doerfelt	2019-08-30	1	-1/+11
* \|	synth: add support for --synth on llvm, link with -lm.	Tristan Gingold	2019-08-30	2	-0/+6
* \|	synth: fix type elaboration of interfaces.	Tristan Gingold	2019-08-30	1	-2/+0
* \|	synth: remove unused const gates.	Tristan Gingold	2019-08-30	2	-13/+5
* \|	vhdl-annotations: ignore conditional variable assignment.	Tristan Gingold	2019-08-30	1	-1/+2
* \|	vhdl-annotate: handle shared anonymous subtype in interfaces.	Tristan Gingold	2019-08-30	1	-1/+4
* \|	synth: ignore report statement.	Tristan Gingold	2019-08-30	1	-0/+2
* \|	vhdl: recognize ieee.numeric_std std_match.	Tristan Gingold	2019-08-30	2	-0/+39
* \|	std_names: add std_match	Tristan Gingold	2019-08-30	2	-3/+5
* \|	vhdl: recognize 1164 condition operator, handle in synth.	Tristan Gingold	2019-08-30	3	-5/+19
* \|	synth: handle enumeration subtype in ranges.	Tristan Gingold	2019-08-30	1	-1/+2
* \|	synth: fix named association in record aggregate.	Tristan Gingold	2019-08-30	1	-1/+3
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*	synth: add support for record types.	Tristan Gingold	2019-08-29	13	-82/+361
*	synth: Integer operators (#902)	marph91	2019-08-28	1	-0/+16
*	synth: support sequential conditional signal assignment.	Tristan Gingold	2019-08-27	2	-0/+3
*	synth: rework partial assignments	Tristan Gingold	2019-08-27	10	-182/+608
*	netlists-disp_vhdl: do not used literals for prefixes.	Tristan Gingold	2019-08-27	1	-12/+53
*	ignore restrict in simulation (#897)	Pepijn de Vos	2019-08-20	2	-18/+17
*	synth: add support for constant exponentiation.	Tristan Gingold	2019-08-20	1	-0/+10
*	synth: set name to assert/assume gates.	Tristan Gingold	2019-08-20	4	-12/+44
*	netlist: fix minor pasto.	Tristan Gingold	2019-08-20	1	-1/+1
*	initial support for reduce and/or (#900)	Pepijn de Vos	2019-08-20	5	-6/+52
*	vhdl psl: fully scan PSL keywords in scanner.	Tristan Gingold	2019-08-20	7	-67/+148
*	vhdl-prints: handle architecture in verification unit hierarchical name.	Tristan Gingold	2019-08-20	1	-0/+7
*	vhdl: handle architecture in verification unit hierarchical name.	Tristan Gingold	2019-08-20	3	-13/+53
*	vhdl-prints: handle verification units.	Tristan Gingold	2019-08-20	1	-318/+354
*	vhdl: handle assume in verification units.	Tristan Gingold	2019-08-20	5	-1/+11
*	synth: analyze input files.	Tristan Gingold	2019-08-20	1	-1/+8
*	synth: set location on assume/assert gates.	Tristan Gingold	2019-08-20	3	-8/+19