iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	synth: fixes for value_const.	Tristan Gingold	2019-10-20	2	-0/+11
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*	vhdl: try to convert identifier to token only for identifiers	Tristan Gingold	2019-10-20	1	-1/+3
\| \| \| \| \|	(and not for bit string literal). Fix #983
*	netlists-memories: fixes in ROM.	Tristan Gingold	2019-10-20	1	-48/+51
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*	netlists-disp_vhdl: display memory initialization value.	Tristan Gingold	2019-10-20	1	-2/+46
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*	synth: add value_const.	Tristan Gingold	2019-10-20	7	-9/+69
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*	netlists-memories: preliminary work to handle ROM.	Tristan Gingold	2019-10-20	1	-111/+194
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*	synth: add more locations.	Tristan Gingold	2019-10-20	2	-0/+2
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*	netlists-dump: also dump instances location.	Tristan Gingold	2019-10-20	1	-6/+34
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*	synth: use note messages for memories (instead of warnings).	Tristan Gingold	2019-10-19	4	-28/+34
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*	ghdlsynth.h: add functions.	Tristan Gingold	2019-10-19	1	-0/+4
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*	Regenerate ghdlsynth_gates.h	Tristan Gingold	2019-10-18	1	-0/+5
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*	netlists-memories: check ports.	Tristan Gingold	2019-10-18	1	-7/+161
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*	vhdl-prints: add parenthesis around boolean and/or.	Tristan Gingold	2019-10-18	1	-0/+4
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*	synth-stmts: ignore EOS in PSL expressions.	Tristan Gingold	2019-10-18	1	-1/+8
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*	syn_interning: add get_index.	Tristan Gingold	2019-10-17	2	-14/+31
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*	netlists-disp_vhdl: display memories.	Tristan Gingold	2019-10-17	1	-1/+97
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*	synth: add netlists-memories to extract memories. Still WIP.	Tristan Gingold	2019-10-17	8	-18/+553
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*	netlists: add remove_instance.	Tristan Gingold	2019-10-16	2	-0/+35
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*	vhdl: check cover/restrict is followed by a sequence.	Tristan Gingold	2019-10-16	4	-11/+65
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*	synth: fix psl cover - test when the final state is reached.	Tristan Gingold	2019-10-15	1	-3/+14
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*	vhdl: Add the implicit [*] at start of PSL cover sequence.	Tristan Gingold	2019-10-15	3	-0/+37
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*	vhdl: handle cover and restrict within vunit.	Tristan Gingold	2019-10-15	5	-1/+17
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*	synth: handle overflow literal.	Tristan Gingold	2019-10-15	2	-1/+9
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*	netlists: declare memory gates.	Tristan Gingold	2019-10-15	3	-3/+215
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*	synth-expr: handle any discrete_range in aggregate choices.	Tristan Gingold	2019-10-15	1	-1/+2
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*	synth-insts: accept architecture instantiation in synth_dependencies.	Tristan Gingold	2019-10-15	1	-2/+3
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*	Use Decode_Work_Option in options. Factorize code.	Tristan Gingold	2019-10-15	4	-25/+11
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*	ghdlsynth: allow --work= option in the middle of files.	Tristan Gingold	2019-10-15	3	-1/+48
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*	synth-inference: handle multiple connections.	Tristan Gingold	2019-10-14	1	-14/+31
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*	synth-infere: extract clock from and tree.	Tristan Gingold	2019-10-14	1	-17/+102
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*	netlists-dump: do not print name of anonymous parameters.	Tristan Gingold	2019-10-14	1	-2/+6
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*	synth-infere: fix partial assignment with clock enable.	Tristan Gingold	2019-10-14	1	-2/+9
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*	vhdl-evaluation: handle bit condition operator. Fix #977	Tristan Gingold	2019-10-13	1	-0/+3
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*	synth: handle constants for condition operator.	Tristan Gingold	2019-10-13	3	-1/+20
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*	synth-stmts: fix thinko (need to adjust type for indexed a 1-bit array).	Tristan Gingold	2019-10-13	1	-2/+5
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*	synth-stmts: handle const indexed array.	Tristan Gingold	2019-10-13	1	-0/+5
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*	synth-oper: handle const array array concat.	Tristan Gingold	2019-10-13	1	-16/+41
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*	synth-oper: add more operations (float div, less for arrays)	Tristan Gingold	2019-10-13	1	-7/+39
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*	synth-stmts: improve support for associations in function calls.	Tristan Gingold	2019-10-13	1	-19/+92
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*	synth-inst: minor refactoring.	Tristan Gingold	2019-10-13	1	-3/+2
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*	synth-oper: handle unsigned unsigned mul.	Tristan Gingold	2019-10-13	1	-0/+13
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*	synth-expr: handle integer type conversion.	Tristan Gingold	2019-10-13	1	-1/+4
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*	synth-expr: handle range array attribute in slices.	Tristan Gingold	2019-10-13	1	-42/+74
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*	vhdl-annotations: handle list of record elements declaration.	Tristan Gingold	2019-10-13	1	-2/+4
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*	vhdl: recognize std_logic_unsigned.conv_integer.	Tristan Gingold	2019-10-13	3	-2/+12
\| \| \| \|	Handle more operators in synth.
*	netlists-iterators: avoid a crash if no ports.	Tristan Gingold	2019-10-13	1	-3/+1
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*	netlists-dump: improve output.	Tristan Gingold	2019-10-13	1	-9/+28
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*	netlists-builders: adjust names of dyn_extract ports.	Tristan Gingold	2019-10-13	1	-2/+2
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*	Show error on wait without condition (#976)	Pepijn de Vos	2019-10-13	1	-0/+4
\| \| \| \| \| \|	* Show error on wait without condition * Null node
*	add record (in)equality (#975)	Pepijn de Vos	2019-10-13	1	-2/+4
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