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* vhdl-std_package: declare missing wildcard typesTristan Gingold2023-03-231-0/+7
* vhdl: make instance_package_body forward_ref, adjustTristan Gingold2023-03-234-4/+5
* vhdl-sem_scopes: avoid duplicate hidden warningTristan Gingold2023-03-221-0/+5
* vhdl: generate and handle package_instantiation_bodyTristan Gingold2023-03-225-11/+108
* vhdl: add Set/Get_Immediate_Body_Flag (for package instantiation)Tristan Gingold2023-03-224-239/+42
* vhdl: add iir_kind_package_instantiation_bodyTristan Gingold2023-03-228-2/+283
* vhdl-canon(canon_declaration): now a procedure, adjustTristan Gingold2023-03-221-40/+12
* trans-chap2: improve support for nested package instantiationTristan Gingold2023-03-222-12/+28
* trans-chap7: partial rewrite of translate_implicit_array_conversionTristan Gingold2023-03-201-49/+169
* vhdl-scanner.adb: avoid a possible crashTristan Gingold2023-03-201-1/+1
* trans-chap3(is_equal_limit): also handle type_mode_e32Tristan Gingold2023-03-151-1/+2
* psl: remove start loops only in case of always.Tristan Gingold2023-03-153-1/+24
* synth_conditiona_signal_assignment: handle simple case directly.Tristan Gingold2023-03-141-46/+79
* ghdldrv: only put direct dependences in gen-makefileTristan Gingold2023-03-133-10/+16
* ghdllocal.adb(Build_Dependence): rebuild file dependencies.Tristan Gingold2023-03-138-433/+404
* synth: support selected signal assignmentTristan Gingold2023-03-091-0/+2
* vhdl: handle selected waveform assignmentTristan Gingold2023-03-093-51/+75
* psl-optimize: add commentsTristan Gingold2023-03-081-1/+6
* psl-disp_nfas: improve outputTristan Gingold2023-03-081-7/+9
* psl-build.adb(build_plus_repeat): fix handling of single edge NFATristan Gingold2023-03-081-3/+15
* Update NEWS and copyright dateTristan Gingold2023-03-061-1/+1
* synth-vhdl_oper: handle to_01. Fix #2372Tristan Gingold2023-03-051-0/+1
* synth-vhdl_stmts: handle unaffected in conditional variable assignmentsTristan Gingold2023-03-021-3/+11
* synth-vhd_oper: handle rising_edge for bit. For #2369Tristan Gingold2023-03-021-8/+11
* synth: handle unaffected in simple sequential signal assignment.Tristan Gingold2023-02-251-4/+9
* grt/Makefile.inc: do not use version-script on FreeBSD.Tristan Gingold2023-02-241-1/+4
* trans-chap2.adb: fix a warningTristan Gingold2023-02-221-1/+0
* synth-vhdl_expr: improve subtype conversionTristan Gingold2023-02-221-69/+160
* vhdl-sem_decls(sem_object_type_from_value): refine.Tristan Gingold2023-02-191-5/+20
* trans-chap2: elaborate dependencies of macro-expanded packages.Tristan Gingold2023-02-191-19/+38
* sem_record_aggregate: add a check for constraints. Fix #2350Tristan Gingold2023-02-131-11/+23
* ghdl: print llvm or gcc backend version with --versionTristan Gingold2023-02-122-2/+6
* ghdllocal, ghdlxml: adjust after previous commit; fix #2349Tristan Gingold2023-02-112-0/+6
* vhdl-sem_lib: units during analysis can depend only on analyzed units.Tristan Gingold2023-02-111-0/+6
* synth-vhdl_eval: handle std_logic_arith.conv_std_logic_vectorTristan Gingold2023-02-093-0/+43
* synth: preliminary work for PSL endpointsTristan Gingold2023-02-082-1/+19
* simul: improve support of PSL endpointsTristan Gingold2023-02-082-10/+12
* simul: improve handling of individual signal associationsTristan Gingold2023-02-081-3/+3
* synth: do not handle null-vectors for to_hstring.Tristan Gingold2023-02-082-1/+18
* trans-chap8: fix a crash while checking bounds in signal assignments.Tristan Gingold2023-02-081-1/+1
* trans-chap8: Fix individual assocs of signal parametersTristan Gingold2023-02-081-22/+44
* simul: handle signal assignment to procedure individual associationsTristan Gingold2023-02-081-8/+19
* trans-chap8: minor reindentationTristan Gingold2023-02-081-1/+1
* synth: use same layout for records in memory as translateTristan Gingold2023-02-0810-70/+229
* vhdl-canon: remove signal parameters for all-sensitized processes.Tristan Gingold2023-02-084-9/+54
* synth: preliminary work to compute access bounds sizeTristan Gingold2023-02-053-2/+128
* elab-vhdl_objtypes: rename acc_bnd_sz to acc_type_szTristan Gingold2023-02-053-7/+7
* vhdl-prints: improve output of generate statementsTristan Gingold2023-02-041-12/+5
* translate: add --no-elaboration flagTristan Gingold2023-02-045-2/+10
* elab-vhdl_debug: handle package in subprogramsTristan Gingold2023-02-041-0/+13
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