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| author | Tristan Gingold <tgingold@free.fr> | 2023-03-02 07:45:19 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-03-02 07:46:41 +0100 |
| commit | c16a0000f9fafd78f0c32a7ed7f28ee537d81d94 (patch) | |
| tree | f988b84ad640926e91701df4db5e02c0f0a082f8 /src | |
| parent | 42478d5795918165766d852870a3d7c00a4ebc93 (diff) | |
| download | ghdl-c16a0000f9fafd78f0c32a7ed7f28ee537d81d94.tar.gz ghdl-c16a0000f9fafd78f0c32a7ed7f28ee537d81d94.tar.bz2 ghdl-c16a0000f9fafd78f0c32a7ed7f28ee537d81d94.zip | |
synth-vhd_oper: handle rising_edge for bit. For #2369
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 07b94fcb2..eb45ae4bb 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -883,6 +883,15 @@ package body Synth.Vhdl_Oper is return Synth_Resize (Ctxt, L, Size, Is_Signed, Expr); end Synth_Conv_Vector; + function Synth_Posedge return Valtyp + is + Edge : Net; + begin + Edge := Build_Posedge (Ctxt, Get_Net (Ctxt, L)); + Set_Location (Edge, Expr); + return Create_Value_Net (Edge, Res_Typ); + end Synth_Posedge; + function Error_Unhandled return Valtyp is begin Error_Msg_Synth @@ -906,7 +915,7 @@ package body Synth.Vhdl_Oper is return Create_Value_Memtyp (Hook_Bit_Rising_Edge.all (L, Res_Typ)); end if; - raise Internal_Error; + return Synth_Posedge; when Iir_Predefined_Bit_Falling_Edge => if Hook_Bit_Falling_Edge /= null then return Create_Value_Memtyp @@ -918,13 +927,7 @@ package body Synth.Vhdl_Oper is return Create_Value_Memtyp (Hook_Std_Rising_Edge.all (L, Res_Typ)); end if; - declare - Edge : Net; - begin - Edge := Build_Posedge (Ctxt, Get_Net (Ctxt, L)); - Set_Location (Edge, Expr); - return Create_Value_Net (Edge, Res_Typ); - end; + return Synth_Posedge; when Iir_Predefined_Ieee_1164_Falling_Edge => if Hook_Std_Falling_Edge /= null then return Create_Value_Memtyp |