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Age
Files
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*
trans.adb: increased maximum identifier length. Fix #1894
Tristan Gingold
2021-10-16
1
-1
/
+1
*
synth: Support PSL declarations in inline PSL
tmeissner
2021-10-14
1
-1
/
+2
*
synth: add support for sequence instance in vunit. Fix #1889
Tristan Gingold
2021-10-13
5
-4
/
+12
*
synth-vhdl_expr.adb: handle more dynamic slice cases. Fix #1886
Tristan Gingold
2021-10-10
1
-42
/
+74
*
synth-vhdl_expr: fix handling of negative factor in slice. For #1886
Tristan Gingold
2021-10-09
1
-25
/
+61
*
synth-vhdl_decls.adb: also detect unassigned variables.
Tristan Gingold
2021-10-09
1
-11
/
+4
*
vhdl-scanner: improve error message. Fix #1883
Tristan Gingold
2021-10-06
1
-1
/
+2
*
version.in: reformatting, simplify the Makefile rule
Tristan Gingold
2021-10-06
1
-7
/
+7
*
elab-order command: add an option to display libraries. Fix #1736
Tristan Gingold
2021-10-04
1
-4
/
+27
*
grt-change_generics: handle subtype for elements. Fix #1386
Tristan Gingold
2021-10-03
1
-2
/
+8
*
vhdl: report unused types and subtypes
Tristan Gingold
2021-10-01
2
-1
/
+13
*
vhdl-formatters: fix bad reformatting on a simple range.
Tristan Gingold
2021-10-01
1
-0
/
+1
*
vhdl: warns on unused component declarations
Tristan Gingold
2021-09-30
2
-1
/
+5
*
grt-vcd.adb: add option --vcd-4states to dump a strict vcd file. Fix #1759
Tristan Gingold
2021-09-30
1
-7
/
+17
*
grt-vcd: exclude arrays from dump. Fix #1881
Tristan Gingold
2021-09-29
1
-59
/
+67
*
netlists-disp_verilog: fix name for memory initialization
Tristan Gingold
2021-09-28
1
-3
/
+4
*
grt-change_generics: handle array subtypes. Fix #1876
Tristan Gingold
2021-09-24
1
-6
/
+20
*
Add parsing of case? statement and simple test.
Brian Padalino
2021-09-24
8
-79
/
+138
*
ghdldrv: use environment variable CC to set the default compiler. For #1629
Tristan Gingold
2021-09-23
1
-3
/
+6
*
vhdl-ieee-vital_timing.adb: handle vhdl 2008. Fix #1875
Tristan Gingold
2021-09-23
1
-3
/
+15
*
vhdl-evaluation.adb: Minor style fixes
Tristan Gingold
2021-09-23
1
-60
/
+61
*
vhdl-sem_assocs.adb: add comments
Tristan Gingold
2021-09-23
1
-10
/
+41
*
Add explicit ?>= and ?> functions for translation.
Brian Padalino
2021-09-22
6
-4
/
+30
*
Implement Matching Operators (#1872)
Brian Padalino
2021-09-22
1
-8
/
+148
*
vhdl-evaluation.adb: handle iir_kind_aggregate in build_constant. Fix #543
Tristan Gingold
2021-09-18
1
-0
/
+11
*
vhdl-parse.adb: minor reformatting
Tristan Gingold
2021-09-18
1
-1
/
+2
*
trans-chap8: fix iteration on an enumeration type with only one literal.
Tristan Gingold
2021-09-18
1
-3
/
+9
*
trans-chap8.adb: refactoring and clean-up. For #1514
Tristan Gingold
2021-09-18
2
-46
/
+12
*
vhdl-sem_names(sem_parenthesis_name): minor refactoring
Tristan Gingold
2021-09-18
1
-13
/
+9
*
vhdl-sem_names(sem_parenthesis_name): handle indexing of delayed attribute.
Tristan Gingold
2021-09-18
1
-2
/
+6
*
configure and Makefile: link ghdl with grt-cstdio
Tristan Gingold
2021-09-17
3
-3
/
+4
*
vhdl-evaluation.adb: fix warning
Tristan Gingold
2021-09-17
1
-3
/
+0
*
vhdl-evaluation: implement to_string for real with format. Fix #874
Tristan Gingold
2021-09-17
1
-23
/
+69
*
vhdl-utils: minor renaming for homogeneity
Tristan Gingold
2021-09-16
2
-2
/
+2
*
trans-chap4: handle unbounded aggregate initial value to unbounded signal.
Tristan Gingold
2021-09-16
1
-1
/
+30
*
Fixed some typos (#1868)
Patrick Lehmann
2021-09-16
11
-22
/
+22
*
netlists-disp_verilog: fix output of parameter assignments. Fix #1866
Tristan Gingold
2021-09-15
1
-12
/
+12
*
netlists-disp_verilog.adb: add 'parameter' before parameters declaration
Tristan Gingold
2021-09-15
1
-1
/
+1
*
synth/netlists-disp_verilog: fix output of parameter values. For #1866
Tristan Gingold
2021-09-15
3
-12
/
+37
*
vhdl: move Get_Source_Identifier to vhdl-utils
Tristan Gingold
2021-09-15
3
-18
/
+25
*
ortho_code-x86-insns: handle OE_ADD R_I_Off + R_I. Fix #1864
Tristan Gingold
2021-09-14
1
-0
/
+7
*
vhdl-sem_expr.adb: adjust aggregate element type extraction. For #737
Tristan Gingold
2021-09-14
1
-2
/
+7
*
trans-chap7: improve handling of vector in aggregates. Fix #1493
Tristan Gingold
2021-09-14
1
-32
/
+58
*
synth-vhdl_oper: handle nor for boolean
Tristan Gingold
2021-09-14
1
-0
/
+1
*
trans-chap3: improve comment
Tristan Gingold
2021-09-14
1
-4
/
+4
*
ortho: for slices, get element size from the result type
Tristan Gingold
2021-09-14
10
-17
/
+76
*
trans-chap7: improve handling of vector in aggregates. Fix #1453
Tristan Gingold
2021-09-12
1
-23
/
+27
*
trans-chap8: fix crash for slice in target aggregate. Fix #786
Tristan Gingold
2021-09-12
1
-0
/
+4
*
vhdl-sem_assocs: add a check to avoid a crash on an error. Fix #873
Tristan Gingold
2021-09-12
1
-0
/
+4
*
vhdl-canon: recurse for default block configuration of a vunit.
Tristan Gingold
2021-09-12
2
-19
/
+25
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