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| author | Tristan Gingold <tgingold@free.fr> | 2021-09-14 04:14:03 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-09-14 04:16:53 +0200 |
| commit | fe9e78d4360d31ed3f8b1873195e7f84b96ebfc2 (patch) | |
| tree | 489c42a3e7b9550e4147b0bc2f0c1c28491d1d06 /src | |
| parent | d6421b108d0b428fa47ec2b9e89053faf0dc7d60 (diff) | |
| download | ghdl-fe9e78d4360d31ed3f8b1873195e7f84b96ebfc2.tar.gz ghdl-fe9e78d4360d31ed3f8b1873195e7f84b96ebfc2.tar.bz2 ghdl-fe9e78d4360d31ed3f8b1873195e7f84b96ebfc2.zip | |
synth-vhdl_oper: handle nor for boolean
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 69213e9f9..d7d73bcec 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -788,6 +788,7 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_1164_Scalar_Or => return Synth_Bit_Dyadic (Id_Or); when Iir_Predefined_Bit_Nor + | Iir_Predefined_Boolean_Nor | Iir_Predefined_Ieee_1164_Scalar_Nor => return Synth_Bit_Dyadic (Id_Nor); when Iir_Predefined_Bit_Nand |