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* elab-vhdl_expr: fix handling of multi-dim arrays. Fix #2144Tristan Gingold2022-07-271-9/+17
* synth-disp_vhdl: improve output for unsigned. Fix #2139Tristan Gingold2022-07-271-2/+17
* elab-vhdl_expr: fix incorrect type of multi-dim array indexing during elabTristan Gingold2022-07-271-0/+9
* synthesis.adb: cleanup after expand. For #2142Tristan Gingold2022-07-271-0/+2
* netlists-disp_vhdl: adjust output for #2140Tristan Gingold2022-07-271-2/+8
* netlists-expands: do not try to clean input of dyn_extract. Fix #2142Tristan Gingold2022-07-271-5/+1
* netlist-disp_vhdl: add a separator between instances and signals.Tristan Gingold2022-07-261-1/+1
* vhdl-parse: set reference_terminal flagTristan Gingold2022-07-261-0/+1
* vhdl-canon: handle conditional variable assignment. Fix #2138Tristan Gingold2022-07-251-1/+16
* simul: gather terminalsTristan Gingold2022-07-254-3/+74
* synth/elab-vhdl_values: add Value_TerminalTristan Gingold2022-07-256-4/+38
* vhdl-nodes: add Get/Set_Reference_Terminal_FlagTristan Gingold2022-07-254-204/+247
* synth-environment: fix memory crash. Fix #2139Tristan Gingold2022-07-251-2/+8
* dyn_tables,tables: add Reserve. For #2139Tristan Gingold2022-07-254-5/+28
* src/simul: rewrite of ghdl/simul based on synthTristan Gingold2022-07-247-0/+3759
* synth: add hook for dot attributeTristan Gingold2022-07-243-7/+17
* vhdl: handle element attribute in declarations. Fix #2136Tristan Gingold2022-07-212-12/+23
* elab-vhdl_decls: elaborate dot attributeTristan Gingold2022-07-213-4/+14
* vhdl-nodes: renaming.Tristan Gingold2022-07-2121-128/+130
* elab-vhdl_decls: elaborate implicit signalsTristan Gingold2022-07-211-2/+23
* Makefile.in: allow build of ghdl_mcode with sundials enabledTristan Gingold2022-07-211-0/+25
* synth-vhdl_expr: add hook for quantitiesTristan Gingold2022-07-202-11/+23
* elab-vhdl_debug: handle signals in packagesTristan Gingold2022-07-201-2/+8
* grt: add analog_solver (work in progress)Tristan Gingold2022-07-204-9/+197
* grt: add real now variable.Tristan Gingold2022-07-204-0/+19
* ghdlsimul: simplify elaboration circuiteryTristan Gingold2022-07-201-13/+0
* elab-vhdl_context: add iterator for top-level packagesTristan Gingold2022-07-202-0/+36
* configure: add --with-sundials (preliminary work)Tristan Gingold2022-07-202-0/+44
* elab-vhdl_debug: disp fp64 valuesTristan Gingold2022-07-204-2/+10
* vhdl-sem_specs: allow protected body in scope of an attribute. Fix #2134Tristan Gingold2022-07-161-0/+2
* vhdl: preliminary work to elaborat quantitiesTristan Gingold2022-07-167-2/+26
* elab-vhdl_values: add Create_Value_QuantityTristan Gingold2022-07-166-2/+41
* grt-types: add Mode_AboveTristan Gingold2022-07-164-7/+15
* vhdl: add Iir_Kinds_AMS_Signal_AttributeTristan Gingold2022-07-164-18/+26
* vhdl-cannon: add Canon_Extract_Sensitivity_Break_StatementTristan Gingold2022-07-162-1/+16
* netlists-inference: add (disabled) code to add a latchTristan Gingold2022-07-161-26/+103
* synth: Display dlatchTristan Gingold2022-07-143-2/+9
* netlists: add d-latchTristan Gingold2022-07-123-2/+38
* Fix access check failed from iir_kind_selected_element (#2132)Michael Nolan2022-07-121-0/+1
* synth-environment: do inference during wire finalizationTristan Gingold2022-07-111-13/+31
* synth-environment: add Loc parameter to Add_Conc_AssignTristan Gingold2022-07-113-4/+13
* netlists-inference: detect false loops only for variables. Fix #2125Tristan Gingold2022-07-111-2/+3
* netlists-disp_verilog: do not connect to null-range output. For #2113Tristan Gingold2022-07-081-41/+47
* vhdl-evaluation: explicitly compute integer_exp to handle overflow.Tristan Gingold2022-07-071-2/+31
* vhdl-evaluation: make overflow_literal non locally static.Tristan Gingold2022-07-072-1/+6
* netlists-disp_verilog: fix output for id_abs. For #2123Tristan Gingold2022-07-061-1/+2
* synth-vhdl_oper: handle is_x for signed/unsigned. Fix #2129Tristan Gingold2022-07-061-1/+3
* Fix issue #2126, add handling of to_ux01 to synthesisMichael Nolan2022-07-051-1/+3
* synth-vhdl_insts: do not crash on unconnected input. Fix #2124Tristan Gingold2022-07-051-0/+4
* netlists-disp_verilog: handle Id_Abs. Fix #2113Tristan Gingold2022-07-041-1/+1
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