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| author | Tristan Gingold <tgingold@free.fr> | 2022-07-14 06:36:36 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-14 06:36:36 +0200 |
| commit | 73e50b2ce5db5a52bf16c2fd5fc754c054b76b48 (patch) | |
| tree | 6b4c69a90f42d22b4760cf2987e3b22debfb0d1c /src | |
| parent | 462c911391b4265e1a8ee2dc5b99bae8232e2daf (diff) | |
| download | ghdl-73e50b2ce5db5a52bf16c2fd5fc754c054b76b48.tar.gz ghdl-73e50b2ce5db5a52bf16c2fd5fc754c054b76b48.tar.bz2 ghdl-73e50b2ce5db5a52bf16c2fd5fc754c054b76b48.zip | |
synth: Display dlatch
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/include/synth_gates.h | 2 | ||||
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 4 | ||||
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 5 |
3 files changed, 9 insertions, 2 deletions
diff --git a/src/synth/include/synth_gates.h b/src/synth/include/synth_gates.h index 78e4a6ef9..20b16ec9b 100644 --- a/src/synth/include/synth_gates.h +++ b/src/synth/include/synth_gates.h @@ -69,7 +69,7 @@ enum Module_Id { Id_Iadff = 67, Id_Mdff = 68, Id_Midff = 69, - Id_Latch = 70, + Id_Dlatch = 70, Id_Tri = 72, Id_Resolver = 73, Id_Utrunc = 82, diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 6bbd87aa3..133959e5f 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -941,6 +941,9 @@ package body Netlists.Disp_Verilog is Disp_Template (" initial" & NL & " \o0 = \i2;" & NL, Inst); end if; + when Id_Dlatch => + Disp_Template (" always @(\i1)" & NL & + " \o0 <= \i0;" & NL, Inst); when Id_Mux2 => Disp_Template (" assign \o0 = \i0 ? \i2 : \i1;" & NL, Inst); when Id_Mux4 => @@ -1199,6 +1202,7 @@ package body Netlists.Disp_Verilog is | Id_Idff | Id_Adff | Id_Iadff + | Id_Dlatch | Id_Isignal => -- As expected Put (" reg "); diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 0b2eb9110..82f8abfc7 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -1056,7 +1056,10 @@ package body Netlists.Disp_Vhdl is " if \ei0 then" & NL & " \o0 <= \i1;" & NL & " end if;" & NL & - " end process;" & NL, Inst); + " end process;" & NL, Inst); + when Id_Dlatch => + Disp_Template + (" \o0 <= \i0 when \fi1 = '1' else \o0;" & NL, Inst); when Id_Mux2 => Disp_Template (" \o0 <= \i1 when \fi0 = '0' else \i2;" & NL, Inst); |