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Author
Age
Files
Lines
*
vhdl-cannon: add Canon_Extract_Sensitivity_Break_Statement
Tristan Gingold
2022-07-16
2
-1
/
+16
*
netlists-inference: add (disabled) code to add a latch
Tristan Gingold
2022-07-16
1
-26
/
+103
*
synth: Display dlatch
Tristan Gingold
2022-07-14
3
-2
/
+9
*
netlists: add d-latch
Tristan Gingold
2022-07-12
3
-2
/
+38
*
Fix access check failed from iir_kind_selected_element (#2132)
Michael Nolan
2022-07-12
1
-0
/
+1
*
synth-environment: do inference during wire finalization
Tristan Gingold
2022-07-11
1
-13
/
+31
*
synth-environment: add Loc parameter to Add_Conc_Assign
Tristan Gingold
2022-07-11
3
-4
/
+13
*
netlists-inference: detect false loops only for variables. Fix #2125
Tristan Gingold
2022-07-11
1
-2
/
+3
*
netlists-disp_verilog: do not connect to null-range output. For #2113
Tristan Gingold
2022-07-08
1
-41
/
+47
*
vhdl-evaluation: explicitly compute integer_exp to handle overflow.
Tristan Gingold
2022-07-07
1
-2
/
+31
*
vhdl-evaluation: make overflow_literal non locally static.
Tristan Gingold
2022-07-07
2
-1
/
+6
*
netlists-disp_verilog: fix output for id_abs. For #2123
Tristan Gingold
2022-07-06
1
-1
/
+2
*
synth-vhdl_oper: handle is_x for signed/unsigned. Fix #2129
Tristan Gingold
2022-07-06
1
-1
/
+3
*
Fix issue #2126, add handling of to_ux01 to synthesis
Michael Nolan
2022-07-05
1
-1
/
+3
*
synth-vhdl_insts: do not crash on unconnected input. Fix #2124
Tristan Gingold
2022-07-05
1
-0
/
+4
*
netlists-disp_verilog: handle Id_Abs. Fix #2113
Tristan Gingold
2022-07-04
1
-1
/
+1
*
synth-vhdl_insts: also handled unbounded records in hash names.
Tristan Gingold
2022-07-02
1
-0
/
+7
*
vhdl-sem_psl: analyze strong properties
Tristan Gingold
2022-07-02
1
-1
/
+2
*
vhdl-sem_names: avoid crash on incorrect selected name.
Tristan Gingold
2022-07-02
1
-6
/
+6
*
vhdl-sem_decls: avoid crash on self use of a generic package.
Tristan Gingold
2022-07-02
1
-0
/
+10
*
vhdl: avoid crash on incorrect use of attributes.
Tristan Gingold
2022-07-02
5
-14
/
+40
*
vhdl: avoid crash on incorrect use of signatures
Tristan Gingold
2022-07-02
3
-281
/
+292
*
vhdl-evaluation: handle more operations (thought synth).
Tristan Gingold
2022-07-02
1
-2
/
+1
*
vhdl-sem_names: avoid duplicate error message. For #2100
Tristan Gingold
2022-06-28
1
-1
/
+19
*
netlists-disp_verilog: adjust, discard null signals. For #2113
Tristan Gingold
2022-06-28
1
-1
/
+6
*
netlists-disp_verilog: fix warning
Tristan Gingold
2022-06-27
1
-1
/
+2
*
synth/netlists-disp_verilog: skip null input port. Fix #2113
Tristan Gingold
2022-06-27
1
-15
/
+20
*
synth: rework #2109 - remove null wires
Tristan Gingold
2022-06-27
8
-26
/
+87
*
synth/netlists-disp_verilog: adjust previous patch. For #2109
Tristan Gingold
2022-06-27
1
-1
/
+2
*
netlists-disp_verilog: do not display ports of width 0. Fix #2109
Tristan Gingold
2022-06-27
1
-5
/
+19
*
Fix nested comments
sudden6
2022-06-26
1
-41
/
+41
*
vhdl-parse: fix crashes after error. Fix #2110
Tristan Gingold
2022-06-26
1
-2
/
+6
*
vhdl-parse_psl: avoid crash on error. For #2110
Tristan Gingold
2022-06-26
1
-1
/
+7
*
trans-chap8: adjust conditions to pass parameters. Fix #2104
Tristan Gingold
2022-06-22
1
-2
/
+9
*
vhdl-sem.adb: avoid a crash on conformance error. Fix #2103
Tristan Gingold
2022-06-21
1
-2
/
+2
*
vhdl-sem_lib: do not disable warnings for files in -c/-r
Tristan Gingold
2022-06-19
1
-1
/
+5
*
trans-chap7: translate anonymous subtype of overflow literal. Fox #2066
Tristan Gingold
2022-06-19
1
-2
/
+6
*
vhdl-sem_expr: check expression index range for aggregate. Fix #2066
Tristan Gingold
2022-06-19
1
-0
/
+25
*
synth-vhdl_insts(synth_single_input_assoc): handle type conversion.
Tristan Gingold
2022-06-16
2
-4
/
+13
*
vhdl-sem.adb(are_trees_equal): handle simple aggregate.
Tristan Gingold
2022-06-16
1
-14
/
+12
*
vhdl/translate: handle inertial association in recursive instantiation
Tristan Gingold
2022-06-16
2
-2
/
+16
*
vhdl-sem_names: handle element and subtype attributes for type conv.
Tristan Gingold
2022-06-16
1
-22
/
+26
*
vhdl-sem_expr: do not attribute element or subtype attributes as expr.
Tristan Gingold
2022-06-16
1
-0
/
+2
*
vhdl: handle 'element in 'range. Fix #2071
Tristan Gingold
2022-06-15
2
-23
/
+104
*
Add comments
Tristan Gingold
2022-06-15
2
-1
/
+2
*
netlists-rename: handle handle signal instances. Fix #2093
Tristan Gingold
2022-06-15
3
-2
/
+28
*
src/synth: add netlists.rename to rename identifiers. Fix #2054
Tristan Gingold
2022-06-14
4
-2
/
+132
*
netlists-disp_verilog: do not display blackboxes. Fix #2092
Tristan Gingold
2022-06-13
1
-0
/
+5
*
netlists-disp_verilog: Use blocking assignments in non-clocked blocks
Anton Blanchard
2022-06-13
1
-10
/
+10
*
vhdl: add a parent field to protected_type_declaration. Fix #2091
Tristan Gingold
2022-06-12
3
-265
/
+271
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