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* synth: allow empty string literal.Tristan Gingold2019-09-122-2/+4
* vhdl-nodes: add a comment.Tristan Gingold2019-09-121-1/+1
* synth: handle unsigned shift rightTristan Gingold2019-09-111-0/+7
* vhdl-ieee-numeric: recognize shift_right.Tristan Gingold2019-09-111-17/+31
* synth: handle unsigned shift left.Tristan Gingold2019-09-115-107/+163
* synth: add synth_compare_sgn_sgnTristan Gingold2019-09-111-0/+23
* synth: handle constant bit compare.Tristan Gingold2019-09-111-0/+6
* synth: handle numeric_std.resize for signed.Tristan Gingold2019-09-111-0/+15
* synth: improve support of return statement.Tristan Gingold2019-09-118-21/+117
* synth: improve support of negative integer values.Tristan Gingold2019-09-112-15/+29
* synth: add const_x gate.Tristan Gingold2019-09-114-1/+27
* synth: introduce Seq_Context.Tristan Gingold2019-09-112-68/+87
* synth: move synth_user_function_call to synth-stmts.Tristan Gingold2019-09-113-60/+62
* synth: improve support of slices.Tristan Gingold2019-09-111-50/+54
* synth: introduce slice type.Tristan Gingold2019-09-114-1/+26
* synth: Add width field in type_type record.Tristan Gingold2019-09-116-109/+119
* synth: handle alias (WIP, read only).Tristan Gingold2019-09-117-12/+86
* vhdl: recognize numeric_std shift_left.Tristan Gingold2019-09-114-3/+31
* synth: add const_sb32, add smul/umul.Tristan Gingold2019-09-076-13/+105
* vhdl: recognize numeric_std mul.Tristan Gingold2019-09-072-0/+27
* synth: handle partial assignments in case statements.Tristan Gingold2019-09-073-44/+95
* synth-expr: fix regression of issue 7Tristan Gingold2019-09-061-1/+2
* synth: abstract of Merge_Assigns.Tristan Gingold2019-09-061-56/+111
* vhdl: fix unused warning on protected variable.Tristan Gingold2019-09-061-0/+1
* vhdl: handle P32 in connect_scalar. Fix #918Tristan Gingold2019-09-051-1/+2
* synth: handle const record aggregates.Tristan Gingold2019-09-054-21/+64
* synth: handle non-constant array aggregates.Tristan Gingold2019-09-052-1/+15
* synth: add netlists.concatsTristan Gingold2019-09-053-31/+140
* synth: add value_const_array.Tristan Gingold2019-09-054-18/+68
* synth-disp_vhdl: handle arrays in disp_out_converter.Tristan Gingold2019-09-051-1/+19
* synth: handle const_bit in disp_constant_inline.Tristan Gingold2019-09-041-0/+4
* synth: handle large width in get_net.Tristan Gingold2019-09-042-4/+14
* vhdl: do not crash on attribute with a type conversion prefix.Tristan Gingold2019-09-041-2/+3
* synth-disp_vhdl: handle records for outputs.Tristan Gingold2019-09-041-42/+76
* synth-disp_vhdl: handle record for input ports.Tristan Gingold2019-09-038-44/+114
* synth: subtype conversion before compare.Tristan Gingold2019-09-031-2/+7
* synth: handle conditional variable assignment.Tristan Gingold2019-09-021-0/+34
* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-028-37/+40
* vhdl synth: recognize more operators (add uns log).Tristan Gingold2019-09-023-9/+62
* synth: remove insert gate.Tristan Gingold2019-08-314-70/+0
* synth: improve synth_uresize.Tristan Gingold2019-08-313-26/+50
* synth: elab subprogram interfaces subtypeTristan Gingold2019-08-311-2/+13
* [PATCH] synth-environment: fix thinkos.Tristan Gingold2019-08-311-14/+57
* synth: add physical division (#904)tgingold2019-08-301-1/+11
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| * synth: added division of physical typeMartin Doerfelt2019-08-301-1/+11
* | synth: add support for --synth on llvm, link with -lm.Tristan Gingold2019-08-302-0/+6
* | synth: fix type elaboration of interfaces.Tristan Gingold2019-08-301-2/+0
* | synth: remove unused const gates.Tristan Gingold2019-08-302-13/+5
* | vhdl-annotations: ignore conditional variable assignment.Tristan Gingold2019-08-301-1/+2
* | vhdl-annotate: handle shared anonymous subtype in interfaces.Tristan Gingold2019-08-301-1/+4
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