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Author
Age
Files
Lines
*
vhdl-sem_decls: handle protected type subtypes
Tristan Gingold
2022-09-25
1
-1
/
+4
*
vhdl-sem_names: handle architecture bodies in sem_denoting_name
Tristan Gingold
2022-09-25
1
-1
/
+2
*
synth-vhdl_stmts: fix missing newline in default assertion messages
Tristan Gingold
2022-09-25
1
-3
/
+3
*
synth: handle default expression for IN variables in assocs
Tristan Gingold
2022-09-25
1
-4
/
+10
*
synth: handle selected names in targets
Tristan Gingold
2022-09-25
1
-1
/
+2
*
synth-vhdl_eval: handle null-null in array concatenations
Tristan Gingold
2022-09-25
1
-0
/
+6
*
simul: gather disconnection specifications, create guard signal
Tristan Gingold
2022-09-25
4
-36
/
+194
*
synth: ignore groups and group templates
Tristan Gingold
2022-09-25
3
-1
/
+15
*
grt: do not initialial GUARD signals on creation.
Tristan Gingold
2022-09-25
1
-1
/
+4
*
synth: handle attribute names
Tristan Gingold
2022-09-25
1
-13
/
+16
*
synth: handle individual subprogram associations for expressions
Tristan Gingold
2022-09-25
1
-55
/
+61
*
simul: handle empty procedures
Tristan Gingold
2022-09-25
1
-1
/
+9
*
synth: rework association conversions
Tristan Gingold
2022-09-25
3
-62
/
+75
*
synth-vhdl_stmts: rework for subprogram associations (WIP)
Tristan Gingold
2022-09-25
1
-57
/
+36
*
synth-vhdl_stmts: support of individual paramater associations (WIP)
Tristan Gingold
2022-09-25
2
-106
/
+238
*
simul: reuse drivers extraction from elaboration
Tristan Gingold
2022-09-25
2
-74
/
+26
*
synth-vhdl_stmts: refactore synth_subprogram_associations
Tristan Gingold
2022-09-25
1
-49
/
+52
*
synth-vhdl_stmts: refactore
Tristan Gingold
2022-09-25
1
-23
/
+32
*
synth-vhdl_stmts: refactoring
Tristan Gingold
2022-09-25
1
-189
/
+208
*
synth-vhdl_stmts: rework in progress of subprogram associations
Tristan Gingold
2022-09-25
1
-108
/
+115
*
synth-vhdl_insts: move pragma unreferenced
Tristan Gingold
2022-09-21
1
-1
/
+2
*
synth: simplify elab-vhdl_annotations
Tristan Gingold
2022-09-19
2
-51
/
+3
*
synth: simplify elab-vhdl_annotations
Tristan Gingold
2022-09-19
5
-197
/
+31
*
synth: rename vhdl.annotations to elab.vhdl_annotations
Tristan Gingold
2022-09-19
8
-18
/
+20
*
synth: rework subprogram associations (WIP)
Tristan Gingold
2022-09-19
3
-42
/
+87
*
synth-vhdl_stmts: minor renaming
Tristan Gingold
2022-09-18
4
-12
/
+12
*
synth: fix assert failure on attribute specification
Tristan Gingold
2022-09-18
1
-1
/
+5
*
simul: handle individual port associations with expressions
Tristan Gingold
2022-09-18
1
-1
/
+5
*
simul: handle type conversions in port associations
Tristan Gingold
2022-09-18
3
-49
/
+57
*
synth: handle open variable association
Tristan Gingold
2022-09-17
1
-22
/
+31
*
simul: fix resolved association
Tristan Gingold
2022-09-17
2
-2
/
+3
*
simul: use synth_declarations for processes and procedures
Tristan Gingold
2022-09-17
4
-18
/
+15
*
synth: factorize code (reuse synth_constant_declaration)
Tristan Gingold
2022-09-17
8
-71
/
+22
*
synth: handle protected types in subprograms
Tristan Gingold
2022-09-17
3
-38
/
+53
*
synth: improve file handling (skip extra data, errors)
Tristan Gingold
2022-09-17
3
-3
/
+53
*
synth: finalize files
Tristan Gingold
2022-09-17
3
-4
/
+30
*
synth: handle read length on text files
Tristan Gingold
2022-09-17
1
-16
/
+40
*
synth: handle incomplete types
Tristan Gingold
2022-09-17
6
-24
/
+87
*
synth: handle individual generic associations
Tristan Gingold
2022-09-17
1
-5
/
+35
*
synth: factorize code with synth_assignment_prefix
Tristan Gingold
2022-09-16
1
-75
/
+15
*
synth: preliminary work to factorize code
Tristan Gingold
2022-09-16
6
-52
/
+69
*
simul: handle active attribute
Tristan Gingold
2022-09-16
4
-11
/
+58
*
synth: handle val attribute for static bit/logic values
Tristan Gingold
2022-09-16
1
-0
/
+3
*
simul: improve support of concurrent procedure call
Tristan Gingold
2022-09-16
1
-1
/
+20
*
simul: improve error handling during elaboration
Tristan Gingold
2022-09-16
2
-5
/
+6
*
synth: improve handling of complex types
Tristan Gingold
2022-09-15
4
-8
/
+30
*
synth: handle vhdl-87 files
Tristan Gingold
2022-09-15
2
-2
/
+14
*
synth: handle access subtypes
Tristan Gingold
2022-09-15
2
-1
/
+9
*
synth: handle read for files of unconstrained arrays
Tristan Gingold
2022-09-15
3
-1
/
+54
*
simul: handle more signals types
Tristan Gingold
2022-09-15
2
-23
/
+128
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